Inventor · disambiguated record
Carl Monzel
Also filed as: MONZEL CARL · MONZEL CARL A · MONZEL III CARL A · MONZEL III CARL ANTHONY
17 granted patents·1 pending application·471 citations·filing 2001–2016
94Inventor score
Top patents by PatentIndex Score
18 records- 0198US8178909B2Integrated circuit cell architecture configurable for memory or logic elementsVENKATRAMAN RAMNATH·Filed 2011·Granted May 15, 2012·115 cites·6 claims
- 0298US8044437B1Integrated circuit cell architecture configurable for memory or logic elementsLSI LOGIC CORP·Filed 2005·Granted Oct 25, 2011·115 cites·12 claims
- 0397US7404154B1Basic cell architecture for structured application-specific integrated circuitsLSI CORP·Filed 2005·Granted Jul 22, 2008·130 cites·16 claims
- 0487US8705268B2Quantifying the read and write margins of memory bit cellsBUER MYRON·Filed 2011·Granted Apr 22, 2014·12 cites·20 claims
- 0583US8429586B2Basic cell architecture for structured ASICsVENKATRAMAN RAMNATH·Filed 2012·Granted Apr 23, 2013·5 cites·5 claims
- 0676US6498758B1Twisted bitlines to reduce coupling effects (dual port memories)LSI LOGIC CORP·Filed 2002·Granted Dec 24, 2002·31 cites·4 claims
- 0774US9753667B2High bandwidth memory and glitch-less differential XORBROADCOM CORP·Filed 2015·Granted Sep 5, 2017·2 cites·16 claims
- 0873US6734744B2SRAM process monitor cellLSI LOGIC CORP·Filed 2002·Granted May 11, 2004·23 cites·18 claims
- 0967US9324451B2All voltage, temperature and process monitor circuit for memoriesBROADCOM CORP·Filed 2014·Granted Apr 26, 2016·3 cites·20 claims
- 1060US6879524B2Memory I/O buffer using shared read/write circuitryLSI LOGIC CORP·Filed 2002·Granted Apr 12, 2005·11 cites·14 claims
- 1150US6864716B2Reconfigurable memory architectureLSI LOGIC CORP·Filed 2003·Granted Mar 8, 2005·6 cites·20 claims
- 1250US6542434B1Programmable self time circuitry for memoriesLSI LOGIC CORP·Filed 2001·Granted Apr 1, 2003·6 cites·25 claims
- 1346US6667912B1Timing scheme for semiconductor memory devicesLSI LOGIC CORP·Filed 2002·Granted Dec 23, 2003·5 cites·12 claims
- 1445US6982891B2Re-configurable content addressable/dual port memoryLSI LOGIC CORP·Filed 2003·Granted Jan 3, 2006·3 cites·18 claims
- 1544US8166440B1Basic cell architecture for structured application-specific integrated circuitsVENKATRAMAN RAMNATH·Filed 2008·Granted Apr 24, 2012·0 cites·6 claims
- 1640US6687183B2Compiled variable internal self time memoryLSI LOGIC CORP·Filed 2001·Granted Feb 3, 2004·4 cites·23 claims
- 1733US2017206948A1Encoded Global Bitlines for Memory and Other CircuitsBROADCOM CORP·Filed 2016·Application pending·0 cites
- 1830US7190185B2Methodology to measure many more transistors on the same test areaLSI LOGIC CORP·Filed 2003·Granted Mar 13, 2007·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →