Memory I/O buffer using shared read/write circuitry

Abstract

A memory input-output (IO) buffer is provided, which includes a bit line, a data input-output line and a combined sense amplifier and write driver. The combined sense amplifier and write driver is coupled to the data input-output line and the first bit line and shares the same physical area on an integrated circuit.

1. A memory input-output (IO) buffer comprising:
 a first bit line;  
 a first data input-output line; and  
 a combined sense amplifier and write driver coupled to the first data input-output line and the first bit line, wherein the memory IO buffer is fabricated on an integrated circuit and the combined sense amplifier and write driver share common semiconductor elements and the same physical area on the integrated circuit.  
 
   
   
     2. The memory IO buffer of  claim 1  and further comprising:
 a column multiplexer element coupled between the combined sense amplifier and write driver and the first bit line.  
 
   
   
     3. The memory IO buffer of  claim 1  wherein the combined sense amplifier and write driver comprises a latching amplifier. 
   
   
     4. The memory IO buffer of  claim 3  wherein the latching amplifier is non-isolated from the bit line such that the first data input-output line is coupled directly to the first bit line. 
   
   
     5. The memory IO buffer of  claim 1  and further comprising:
 a second bit line, wherein the first and second bit lines form a complementary bit line pair;  
 a second data input-output line wherein the first and second data input-output lines form a complementary data input-output line pair; and  
 wherein the combined sense amplifier and write driver is coupled between the complementary bit line pair and between the complementary data input-output line pair.  
 
   
   
     6. The memory IO buffer of  claim 5  wherein the combined sense amplifier and write driver comprises:
 first and second cross-coupled inverters coupled between the first and second bit lines and between the first and second data input-output lines.  
 
   
   
     7. The memory IO buffer of  claim 6  and further comprising a read sense and write drive enable circuit, wherein the first and second cross-coupled inverters are biased between first and second voltage supply terminals, and the read sense and write drive enable circuit is coupled in a bias path between the cross-coupled inverters and the second voltage supply terminal. 
   
   
     8. The memory IO buffer of  claim 7  wherein the read sense and write drive enable circuit comprises:
 a sense enable input;  
 a write enable input;  
 a sense enable transistor coupled in series between the first and second cross-coupled inverters and the second voltage supply terminal and having a control terminal coupled to the sense enable input; and  
 a write enable transistor coupled in series between the first and second cross-coupled inverters and the second voltage supply terminal and having a control terminal coupled to the write enable input.  
 
   
   
     9. A combined sense amplifier and write driver circuit comprising:
 first and second complementary bit lines;  
 first and second complementary data input-output lines; and  
 a selectively enabled latching amplifier coupled to the first and second complementary bit lines and the first and second complementary data input-output lines, wherein the latching amplifier is enabled during a read state and a write state and is disabled during an idle state.  
 
   
   
     10. The circuit of  claim 9  wherein the latching amplifier is non-isolated from the first and second complementary bit lines such that the first data input-output line is coupled directly to the first bit line and the second data input-output line is coupled directly to the second bit line. 
   
   
     11. The circuit of  claim 9  wherein the latching amplifier comprises:
 first and second cross-coupled inverters coupled between the first and second complementary bit lines and between the first and second complementary data input-output lines.  
 
   
   
     12. The circuit of  claim 11  and further comprising a read sense and write drive enable circuit, wherein the first and second cross-coupled inverters are biased between first and second voltage supply terminals, and the read sense and write drive enable circuit is coupled in a bias path between the cross-coupled inverters and the second voltage supply terminal. 
   
   
     13. The circuit of  claim 12  wherein the read sense and write drive enable circuit comprises:
 a sense enable input;  
 a write enable input;  
 a sense enable transistor coupled in series between the first and second cross-coupled inverters and the second voltage supply terminal and having a control terminal coupled to the sense enable input; and  
 a write enable transistor coupled in series between the first and second cross-coupled inverters and the second voltage supply terminal and having a control terminal coupled to the write enable input.  
 
   
   
     14. A memory input-output (IO) buffer comprising:
 first and second complementary bit lines;  
 first and second complementary data input-output lines;  
 a column multiplexer element coupled to the complementary bit lines; and  
 combined read sense and write driver means, coupled between the column multiplexer element and the complementary data input-output lines, for sensing voltages on the complementary bit lines through the column multiplexer element during a read state and for driving voltages on the complementary bit lines through the column multiplexer element during a write state.