Inventor · disambiguated record
Joseph A. Iadanza
Also filed as: IADANZA JOSEPH · IADANZA JOSEPH A · IADANZA JOSEPH ANDREW · LARAMIE MICHAEL JOSEPH
90 granted patents·11 pending applications·3,810 citations·filing 1995–2022
99Inventor score
Top patents by PatentIndex Score
101 records- 0199US6233191B1Field programmable memory arrayIBM·Filed 2000·Granted May 15, 2001·205 cites·22 claims
- 0299US6091645AProgrammable read ports and write ports for I/O buses in a field programmable memory arrayIBM·Filed 1998·Granted Jul 18, 2000·189 cites·19 claims
- 0399US5646544ASystem and method for dynamically reconfiguring a programmable gate arrayIBM·Filed 1995·Granted Jul 8, 1997·402 cites·17 claims
- 0498US6130854AProgrammable address decoder for field programmable memory arrayIBM·Filed 1998·Granted Oct 10, 2000·181 cites·21 claims
- 0598US6118707AMethod of operating a field programmable memory array with a field programmable gate arrayIBM·Filed 1998·Granted Sep 12, 2000·174 cites·2 claims
- 0698US6038192AMemory cells for field programmable memory arrayIBM·Filed 1998·Granted Mar 14, 2000·193 cites·13 claims
- 0798US6023421ASelective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory arrayIBM·Filed 1998·Granted Feb 8, 2000·222 cites·23 claims
- 0897US6044031AProgrammable bit line drive modes for memory arraysIBM·Filed 1998·Granted Mar 28, 2000·225 cites·4 claims
- 0997US5914906AField programmable memory arrayIBM·Filed 1995·Granted Jun 22, 1999·210 cites·20 claims
- 1097US5745422ACross-coupled bitline segments for generalized data propagationIBM·Filed 1996·Granted Apr 28, 1998·194 cites·30 claims
- 1197US5631578AProgrammable array interconnect networkIBM·Filed 1995·Granted May 20, 1997·212 cites·29 claims
- 1296US8841893B2Dual-loop voltage regulator architecture with high DC accuracy and fast response timeBULZACCHELLI JOHN F·Filed 2011·Granted Sep 23, 2014·24 cites·25 claims
- 1396US6075745AField programmable memory arrayIBM·Filed 1998·Granted Jun 13, 2000·195 cites·8 claims
- 1496US5802003ASystem for implementing write, initialization, and reset in a memory array using a single cell write portIBM·Filed 1995·Granted Sep 1, 1998·177 cites·38 claims
- 1592US7408800B1Apparatus and method for improved SRAM device performance through double gate topologyIBM·Filed 2007·Granted Aug 5, 2008·25 cites·3 claims
- 1692US7000214B2Method for designing an integrated circuit having multiple voltage domainsIBM·Filed 2003·Granted Feb 14, 2006·79 cites·20 claims
- 1792US5719889AProgrammable parity checking and comparison circuitIBM·Filed 1995·Granted Feb 17, 1998·189 cites·19 claims
- 1891US11451234B1Delay looked loop circuit and method of measuring delayNANYA TECHNOLOGY CORP·Filed 2021·Granted Sep 20, 2022·6 cites·20 claims
- 1991US8793365B2Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodesARSOVSKI IGOR·Filed 2009·Granted Jul 29, 2014·26 cites·28 claims
- 2091US7483806B1Design structures, method and systems of powering on integrated circuitIBM·Filed 2007·Granted Jan 27, 2009·23 cites·16 claims
- 2189US7307467B2Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devicesIBM·Filed 2006·Granted Dec 11, 2007·13 cites·12 claims
- 2288US5949719AField programmable memory arrayIBM·Filed 1998·Granted Sep 7, 1999·90 cites·34 claims
- 2385US7429877B2Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution pathIBM·Filed 2007·Granted Sep 30, 2008·12 cites·23 claims
- 2483US8643987B2Current leakage in RC ESD clampsCHU ALBERT M·Filed 2012·Granted Feb 4, 2014·6 cites·18 claims
- 2583US7710302B2Design structures and systems involving digital to analog convertersIBM·Filed 2007·Granted May 4, 2010·14 cites·14 claims
- 2683US5646546AProgrammable logic cell having configurable gates and multiplexersIBM·Filed 1995·Granted Jul 8, 1997·40 cites·38 claims
- 2782US7932774B2Structure for intrinsic RC power distribution for noise filtering of analog suppliesIBM·Filed 2008·Granted Apr 26, 2011·12 cites·14 claims
- 2882US7643591B2Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical designIBM·Filed 2006·Granted Jan 5, 2010·10 cites·20 claims
- 2982US7511528B2Device and method to eliminate step response power supply perturbationIBM·Filed 2006·Granted Mar 31, 2009·11 cites·15 claims
- 3082US6487701B1System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technologyIBM·Filed 2000·Granted Nov 26, 2002·27 cites·39 claims
- 3181US11601118B1Latch device and operation method thereofNANYA TECHNOLOGY CORP·Filed 2021·Granted Mar 7, 2023·1 cites·18 claims
- 3281US7362138B1Flexible multimode logic element for use in a configurable mixed-logic signal distribution pathIBM·Filed 2006·Granted Apr 22, 2008·10 cites·19 claims
- 3380US8988140B2Real-time adaptive voltage control of logic blocksIBM·Filed 2013·Granted Mar 24, 2015·5 cites·19 claims
- 3480US7403039B1Flexible multimode logic element for use in a configurable mixed-logic signal distribution pathIBM·Filed 2007·Granted Jul 22, 2008·9 cites·20 claims
- 3579US7716007B2Design structures of powering on integrated circuitIBM·Filed 2008·Granted May 11, 2010·8 cites·7 claims
- 3678US7793237B2System, structure and method of providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structureIBM·Filed 2007·Granted Sep 7, 2010·5 cites·22 claims
- 3778US7729159B2Apparatus for improved SRAM device performance through double gate topologyIBM·Filed 2008·Granted Jun 1, 2010·9 cites·17 claims
- 3877US7823107B2Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical designIBM·Filed 2007·Granted Oct 26, 2010·8 cites·20 claims
- 3977US7089512B2Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuitsIBM·Filed 2004·Granted Aug 8, 2006·23 cites·22 claims
- 4077US5781032AProgrammable inverter circuit used in a programmable logic cellIBM·Filed 1996·Granted Jul 14, 1998·36 cites·4 claims
- 4176US6960837B2Method of connecting core I/O pins to backside chip I/O padsIBM·Filed 2002·Granted Nov 1, 2005·23 cites·19 claims
- 4275US7770139B2Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution pathIBM·Filed 2007·Granted Aug 3, 2010·6 cites·5 claims
- 4374US7268632B2Structure and method for providing gate leakage isolation locally within analog circuitsIBM·Filed 2005·Granted Sep 11, 2007·8 cites·15 claims
- 4473US7868809B2Digital to analog converter having fastpathsIBM·Filed 2009·Granted Jan 11, 2011·8 cites·16 claims
- 4572US6636995B1Method of automatic latch insertion for testing application specific integrated circuitsIBM·Filed 2000·Granted Oct 21, 2003·17 cites·18 claims
- 4670US6545521B2Low skew, power sequence independent CMOS receiver deviceIBM·Filed 2001·Granted Apr 8, 2003·15 cites·11 claims
- 4770US5651013AProgrammable circuits for test and operation of programmable gate arraysIBM·Filed 1995·Granted Jul 22, 1997·32 cites·29 claims
- 4869US11016144B2Testing integrated circuit designs containing multiple phase rotatorsIBM·Filed 2020·Granted May 25, 2021·0 cites·20 claims
- 4968US7821053B2Tunable capacitorIBM·Filed 2006·Granted Oct 26, 2010·4 cites·8 claims
- 5068US7218135B2Method and apparatus for reducing noise in a dynamic mannerIBM·Filed 2005·Granted May 15, 2007·5 cites·20 claims
Showing the top 50 of 101 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →