Inventor · disambiguated record
Kiyoaki Hashimoto
Also filed as: HASHIMOTO KIYOAKI
18 granted patents·3 pending applications·326 citations·filing 2011–2023
93Inventor score
Top patents by PatentIndex Score
21 records- 0198US9224717B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA INC·Filed 2014·Granted Dec 29, 2015·76 cites·20 claims
- 0298US9093435B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA INC·Filed 2013·Granted Jul 28, 2015·68 cites·23 claims
- 0398US8618659B2Package-on-package assembly with wire bonds to encapsulation surfaceSATO HIROAKI·Filed 2012·Granted Dec 31, 2013·147 cites·38 claims
- 0497US11830845B2Package-on-package assembly with wire bonds to encapsulation surfaceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Nov 28, 2023·4 cites·19 claims
- 0592US9137903B2Semiconductor chip assembly and method for making sameKANG TECK-GYU·Filed 2011·Granted Sep 15, 2015·13 cites·20 claims
- 0691US10062661B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA INC·Filed 2017·Granted Aug 28, 2018·5 cites·14 claims
- 0785US11424211B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA LLC·Filed 2020·Granted Aug 23, 2022·1 cites·29 claims
- 0881US9786611B2Method for manufacturing a semiconductor packageJ-DEVICES CORP·Filed 2016·Granted Oct 10, 2017·4 cites·15 claims
- 0977US10593643B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA INC·Filed 2018·Granted Mar 17, 2020·1 cites·14 claims
- 1075US8890304B2Fan-out microelectronic unit WLP having interconnects comprising a matrix of a high melting point, a low melting point and a polymer materialSATO HIROAKI·Filed 2011·Granted Nov 18, 2014·3 cites·21 claims
- 1172US12494453B2Package-on-package assembly with wire bonds to encapsulation surfaceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Dec 9, 2025·0 cites·16 claims
- 1272US10833044B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA INC·Filed 2020·Granted Nov 10, 2020·0 cites·18 claims
- 1371US10090276B2Semiconductor package to reduce warpingJ DEVICES CORP·Filed 2015·Granted Oct 2, 2018·2 cites·8 claims
- 1470US9691731B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA INC·Filed 2015·Granted Jun 27, 2017·1 cites·20 claims
- 1560US8525338B2Chip with sintered connections to packageSATO HIROAKI·Filed 2011·Granted Sep 3, 2013·1 cites·22 claims
- 1657US9337165B2Method for manufacturing a fan-out WLP with packageTESSERA INC·Filed 2014·Granted May 10, 2016·0 cites·17 claims
- 1752US9716075B2Semiconductor chip assembly and method for making sameTESSERA INC·Filed 2015·Granted Jul 25, 2017·0 cites·11 claims
- 1852US2017309593A1Semiconductor chip assembly and method for making sameTESSERA INC·Filed 2017·Application pending·0 cites
- 1949US2016254247A1Fan-out WLP with packageTESSERA INC·Filed 2016·Application pending·0 cites
- 2045US9418944B2Semiconductor packageJ-DEVICES CORP·Filed 2015·Granted Aug 16, 2016·0 cites·11 claims
- 2136US2017207157A1Method for manufacturing semiconductor package, and semiconductor packageJ-DEVICES CORP·Filed 2016·Application pending·0 cites
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