Inventor · disambiguated record
Xintuo Dai
Also filed as: DAI XINTUO
21 granted patents·3 pending applications·79 citations·filing 2010–2022
93Inventor score
Top patents by PatentIndex Score
24 records- 0197US9620380B1Methods for fabricating integrated circuits using self-aligned quadruple patterningGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 11, 2017·31 cites·18 claims
- 0293US10705435B2Self-referencing and self-calibrating interference pattern overlay measurementGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 7, 2020·8 cites·18 claims
- 0393US9991361B2Methods for performing a gate cut last scheme for FinFET semiconductor devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 5, 2018·9 cites·20 claims
- 0492US11675277B2Self-referencing and self-calibrating interference pattern overlay measurementKLA CORP·Filed 2021·Granted Jun 13, 2023·2 cites·40 claims
- 0591US10635007B1Apparatus and method for aligning integrated circuit layers using multiple grating materialsGLOBALFOUNDRIES INC·Filed 2018·Granted Apr 28, 2020·11 cites·16 claims
- 0688US10062772B2Preventing bridge formation between replacement gate and source/drain region through STI structureGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 28, 2018·5 cites·10 claims
- 0786US9812324B1Methods to control fin tip placementGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 7, 2017·4 cites·14 claims
- 0876US9780002B1Threshold voltage and well implantation method for semiconductor devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 3, 2017·2 cites·20 claims
- 0976US9329471B1Achieving a critical dimension target based on resist characteristicsGLOBALFOUNDRIES INC·Filed 2014·Granted May 3, 2016·2 cites·16 claims
- 1071US9329495B2Overlay metrology system and methodGLOBALFOUNDRIES INC·Filed 2013·Granted May 3, 2016·2 cites·20 claims
- 1169US9640402B1Methods for gate formation in circuit structuresGLOBALFOUNDRIES INC·Filed 2016·Granted May 2, 2017·1 cites·20 claims
- 1268US11231654B2Self-referencing and self-calibrating interference pattern overlay measurementGLOBALFOUNDRIES US INC·Filed 2020·Granted Jan 25, 2022·0 cites·19 claims
- 1368US9698018B1Introducing self-aligned dopants in semiconductor finsGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 4, 2017·1 cites·20 claims
- 1467US9606432B2Alternating space decomposition in circuit structure fabricationGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 28, 2017·1 cites·16 claims
- 1555US9947545B2Methods for gate formation in circuit structuresGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 17, 2018·0 cites·20 claims
- 1654US2023066543A1Fully self aligned via integration processesAPPLIED MATERIALS INC·Filed 2022·Application pending·0 cites
- 1753US10833022B2Structure and method to improve overlay performance in semiconductor devicesGLOBALFOUNDRIES INC·Filed 2019·Granted Nov 10, 2020·0 cites·6 claims
- 1851US10809633B1Overlay control with corrections for lens aberrationsGLOBALFOUNDRIES INC·Filed 2019·Granted Oct 20, 2020·0 cites·4 claims
- 1950US10504851B2Structure and method to improve overlay performance in semiconductor devicesGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 10, 2019·0 cites·20 claims
- 2045US10483214B2Overlay structuresGLOBALFOUNDRIES INC·Filed 2018·Granted Nov 19, 2019·0 cites·14 claims
- 2140US9627274B1Methods of forming self-aligned contacts on FinFET devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 18, 2017·0 cites·22 claims
- 2239US10056458B2Siloxane and organic-based MOL contact patterningGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 21, 2018·0 cites·19 claims
- 2336US2011263052A1Method of removing contaminationsDAI XINTUO·Filed 2010·Application pending·0 cites
- 2434US2017162430A1Methods for producing integrated circuits with air gaps and integrated circuits produced from such methodsGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →