Inventor · disambiguated record
John Fernando
Also filed as: FERNANDO JOHN · FERNANDO JOHN S · FERNANDO JOHN SUSANTHA
23 granted patents·3 pending applications·884 citations·filing 1988–2018
96Inventor score
Files withAGERE SYSTEMS INC5AGERE SYST GUARDIAN CORP4INTEL CORP4LUCENT TECHNOLOGIES INC4ORACLE INT CORP4
Top patents by PatentIndex Score
26 records- 0195US6272616B1Method and apparatus for executing multiple instruction streams in a digital processor with multiple data pathsAGERE SYST GUARDIAN CORP·Filed 1998·Granted Aug 7, 2001·382 cites·48 claims
- 0291US5025365AHardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessorsUNISYS CORP·Filed 1988·Granted Jun 18, 1991·138 cites·11 claims
- 0385US6397240B1Programmable accelerator for a programmable processor systemAGERE SYST GUARDIAN CORP·Filed 1999·Granted May 28, 2002·125 cites·61 claims
- 0480US6052766APointer register indirectly addressing a second register in the processor core of a digital processorLUCENT TECHNOLOGIES INC·Filed 1998·Granted Apr 18, 2000·103 cites·19 claims
- 0574US6874056B2Method and apparatus for reducing cache thrashingAGERE SYSTEMS INC·Filed 2001·Granted Mar 29, 2005·19 cites·30 claims
- 0669US10152436B2Mutual exclusion in a non-coherent memory hierarchyORACLE INT CORP·Filed 2016·Granted Dec 11, 2018·1 cites·20 claims
- 0767US7383455B2Method and apparatus for transferring multi-source/multi-sink control signals using a differential signaling techniqueAGERE SYSTEMS INC·Filed 2007·Granted Jun 3, 2008·3 cites·23 claims
- 0865US6269440B1Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneouslyAGERE SYST GUARDIAN CORP·Filed 1999·Granted Jul 31, 2001·51 cites·46 claims
- 0960US7353513B2Method and apparatus for establishing a bound on the effect of task interference in a cache memoryAGERE SYSTEMS INC·Filed 2002·Granted Apr 1, 2008·6 cites·16 claims
- 1059US10509740B2Mutual exclusion in a non-coherent memory hierarchyORACLE INT CORP·Filed 2018·Granted Dec 17, 2019·0 cites·20 claims
- 1156US7346735B2Virtualized load buffersINTEL CORP·Filed 2004·Granted Mar 18, 2008·4 cites·16 claims
- 1252US6874057B2Method and apparatus for cache space allocationAGERE SYSTEMS INC·Filed 2001·Granted Mar 29, 2005·2 cites·30 claims
- 1351US6754748B2Method and apparatus for distributing multi-source/multi-sink control signals among nodes on a chipAGERE SYSTEMS INC·Filed 2001·Granted Jun 22, 2004·2 cites·21 claims
- 1449US8478944B2Method and apparatus for adaptive cache frame locking and unlockingDWYER HARRY·Filed 2012·Granted Jul 2, 2013·0 cites·12 claims
- 1548US8261022B2Method and apparatus for adaptive cache frame locking and unlockingDWYER HARRY·Filed 2001·Granted Sep 4, 2012·2 cites·20 claims
- 1646US8191067B2Method and apparatus for establishing a bound on the effect of task interference in a cache memoryBETKER MICHAEL RICHARD·Filed 2008·Granted May 29, 2012·0 cites·12 claims
- 1746US7533232B2Accessing data from different memory locations in the same cycleINTEL CORP·Filed 2003·Granted May 12, 2009·0 cites·28 claims
- 1845US7577791B2Virtualized load buffersINTEL CORP·Filed 2007·Granted Aug 18, 2009·0 cites·17 claims
- 1945US5802360ADigital microprocessor device having dnamically selectable instruction execution intervalsLUCENT TECHNOLOGIES INC·Filed 1996·Granted Sep 1, 1998·17 cites·26 claims
- 2041US5761492AMethod and apparatus for uniform and efficient handling of multiple precise events in a processor by including event commands in the instruction setLUCENT TECHNOLOGIES INC·Filed 1996·Granted Jun 2, 1998·14 cites·44 claims
- 2138US5805489ADigital microprocessor device having variable-delay division hardwareLUCENT TECHNOLOGIES INC·Filed 1996·Granted Sep 8, 1998·11 cites·32 claims
- 2238US2002124199A1Method and apparatus for transferring multi-source/multi-sink control signals using a differential signaling techniqueFiled 2001·Application pending·0 cites
- 2334US2007136564A1Method and apparatus to save and restore context using scan cellsINTEL CORP·Filed 2005·Application pending·0 cites
- 2433US9678872B2Memory paging for processors using physical addressesORACLE INT CORP·Filed 2015·Granted Jun 13, 2017·0 cites·20 claims
- 2533US6434163B1Transverse correlator structure for a rake receiverAGERE SYST GUARDIAN CORP·Filed 1998·Granted Aug 13, 2002·4 cites·21 claims
- 2633US2018349280A1Snoop filtering for multi-processor-core systemsORACLE INT CORP·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →