Method and apparatus for transferring multi-source/multi-sink control signals using a differential signaling technique

Abstract

A method and apparatus are disclosed for transferring multi-source/multi-sink control signals using a differential signaling technique. An “active” state is transferred on a multi-source/multi-sink control signal network by inverting the previous voltage level, and an “inactive state” is transferred by maintaining the previous level. A change in the voltage level associated with a given control signal indicates that at least one node on an SoC device is asserting the corresponding control signal. In order to detect a change in the signal state from a previous cycle, each node includes a memory element, such as a latch, for maintaining the previous state. In this manner, a voltage level from the next interval can be compared to the recorded state to detect a change of state indicating an assertion of the control signal by another node. Thus, a given control signal is asserted whenever the state of the signal at the end of the previous cycle is different from the state of the signal at the end of the proceeding cycle. In one exemplary implementation, the asserted control signal is applied to an exclusive-OR gate together with the current value on the control signal wire to thereby cause a transition indicating an assertion of the control signal.

We claim:  
     
         1 . A method for transmitting a control signal on a bus, said control signal having two signal states, said method comprising the steps of: 
 transferring a first signal state for said control signal by adjusting a voltage level from a previous time interval; and    transferring a second signal state by maintaining said voltage level from the previous time interval.    
     
     
         2 . The method of  claim 1 , further comprising the step of maintaining said voltage level from the previous time interval using a memory element.  
     
     
         3 . The method of  claim 1 , further comprising the step of ensuring that only a single node connected to said bus can assert said control signal in a given time interval.  
     
     
         4 . The method of  claim 1 , wherein said bus is on a system-on-chip (SoC).  
     
     
         5 . The method of  claim 1 , wherein said bus is on a printed circuit board (PCB).  
     
     
         6 . The method of  claim 1 , wherein said adjusting step further comprises the step of transitioning from a first voltage level to a second voltage level.  
     
     
         7 . The method of  claim 1 , wherein said adjusting step further comprises the step of applying a high logic level to an exclusive-OR gate with said voltage level from the previous time interval to determine the signal level to be asserted in the current time interval.  
     
     
         8 . A method for receiving a control signal on a bus, said control signal having two signal states, said method comprising the steps of: 
 detecting a first signal state for said control signal if a voltage level from a previous time interval is adjusted; and    detecting a second signal state if said voltage level from the previous time interval is maintained.    
     
     
         9 . The method of  claim 8 , further comprising the step of maintaining said control signal value at said voltage level from said previous time interval when no node drives said bus.  
     
     
         10 . The method of  claim 9 , further comprising the step of compensating for leakage and cross-coupling effects.  
     
     
         11 . The method of  claim 8 , further comprising the step of maintaining said voltage level from the previous time interval using a memory element.  
     
     
         12 . The method of  claim 8 , wherein said bus is on a system-on-chip (SoC).  
     
     
         13 . The method of  claim 8 , wherein said bus is on a printed circuit board (PCB).  
     
     
         14 . The method of  claim 8 , wherein said adjusted voltage level is a transitioning from a first voltage level to a second voltage level.  
     
     
         15 . The method of  claim 8 , wherein said first detecting step further comprises the step of applying said received control signal state to an exclusive-OR gate with said voltage level from the previous time interval to determine the signal level to be asserted in the current time interval.  
     
     
         16 . A device for communicating a control signal on a bus, said control signal having two signal states, said device comprising: 
 a memory element for maintaining a voltage level from a previous time interval;    a comparison circuit for detecting a change in said voltage level from the previous time interval indicating an assertion of said control signal by another device; and    an adjustment circuit for changing said voltage level from the previous time interval indicating an assertion of said control signal by another device.    
     
     
         17 . The device of  claim 16 , wherein said memory element is a latch.  
     
     
         18 . The device of  claim 16 , further comprising a circuit that ensures that only a single device connected to said bus can assert said control signal in a given time interval.  
     
     
         19 . The device of  claim 16 , wherein said bus is on a system-on-chip (SoC).  
     
     
         20 . The device of  claim 16 , wherein said bus is on a printed circuit board (PCB).  
     
     
         21 . The device of  claim 16 , wherein said change in said voltage level from the previous time interval is a change from a first voltage level to a second voltage level.  
     
     
         22 . The device of  claim 16 , wherein said adjustment circuit is an exclusive-OR gate.  
     
     
         23 . The device of  claim 16 , wherein said comparison circuit is an exclusive-OR gate.