Inventor · disambiguated record
Weidan Li
Also filed as: LI WEIDAN
15 granted patents·1 pending application·427 citations·filing 1998–2015
93Inventor score
Top patents by PatentIndex Score
16 records- 0196US6423628B1Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal linesLSI LOGIC CORP·Filed 1999·Granted Jul 23, 2002·218 cites·11 claims
- 0288US7321254B2On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation methodLSI LOGIC CORP·Filed 2004·Granted Jan 22, 2008·39 cites·4 claims
- 0381US6608365B1Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cellsLSI LOGIC CORP·Filed 2002·Granted Aug 19, 2003·29 cites·16 claims
- 0477US6391768B1Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structureLSI LOGIC CORP·Filed 2000·Granted May 21, 2002·28 cites·2 claims
- 0575US6807656B1Decoupling capacitance estimation and insertion flow for ASIC designsLSI LOGIC CORP·Filed 2003·Granted Oct 19, 2004·28 cites·27 claims
- 0671US7000163B1Optimized buffering for JTAG boundary scan netsLSI LOGIC CORP·Filed 2002·Granted Feb 14, 2006·17 cites·16 claims
- 0770US6756674B1Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making sameLSI LOGIC CORP·Filed 1999·Granted Jun 29, 2004·36 cites·24 claims
- 0869US8946890B2Power/ground layout for chipsSUTARDJA SEHAT·Filed 2011·Granted Feb 3, 2015·2 cites·15 claims
- 0966US6569751B1Low via resistance systemLSI LOGIC CORP·Filed 2000·Granted May 27, 2003·9 cites·17 claims
- 1057US8921938B1Laterally diffused metal oxide semiconductor (LDMOS) device with overlapping wellsMARVELL INT LTD·Filed 2013·Granted Dec 30, 2014·1 cites·16 claims
- 1156US9449709B1Volatile memory and one-time program (OTP) compatible memory cell and programming methodQUALCOMM INC·Filed 2015·Granted Sep 20, 2016·1 cites·20 claims
- 1254US6794756B2Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal linesLSI LOGIC CORP·Filed 2002·Granted Sep 21, 2004·5 cites·4 claims
- 1345US6329720B1Tungsten local interconnect for silicon integrated circuit structures, and method of making sameLSI LOGIC CORP·Filed 1998·Granted Dec 11, 2001·13 cites·11 claims
- 1444US7181712B2Method of optimizing critical path delay in an integrated circuit designLSI LOGIC CORP·Filed 2004·Granted Feb 20, 2007·1 cites·4 claims
- 1544US2015155202A1Power/ground layout for chipsMARVELL WORLD TRADE LTD·Filed 2015·Application pending·0 cites
- 1642US6893962B2Low via resistance systemLSI LOGIC CORP·Filed 2003·Granted May 17, 2005·0 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →