Power/ground layout for chips

Abstract

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

What is claimed is: 
     
         1 . A method of fabricating a chip, the method comprising:
 forming a base metal layer over a first semiconductor die;   forming a first metal layer that is separate from the base metal layer;   creating a first island in the first metal layer to route at least one of (i) a ground signal or (ii) a power signal in the first semiconductor die, wherein the first island is defined by an opening in the first metal layer that surrounds the first island;   forming a second metal layer that is separate from the first metal layer; and   creating a second island in the second metal layer to route at least one of (i) the ground signal or (ii) the power signal in the first semiconductor die, wherein the second island is defined by an opening in the second metal layer that surrounds the second island.   
     
     
         2 . The method of  claim 1 , further comprising:
 prior to forming the second metal layer, placing a dielectric material (i) on the first metal layer and (ii) in the opening in the first metal layer such that the first island in the first metal layer is surrounded along the entire periphery of the first island by the dielectric material.   
     
     
         3 . The method of  claim 2 , further comprising:
 placing a passivation material (i) on the second metal layer and (ii) in the opening in the second metal layer such that the second island in the second metal layer is surrounded along the entire periphery of the second island by the passivation material.   
     
     
         4 . The method of  claim 3 , wherein placing the passivation material on the second metal layer forms a passivation layer, and wherein the method further comprises:
 forming openings in the passivation layer to expose portions of the second metal layer.   
     
     
         5 . The method of  claim 3 , wherein placing the passivation material on the second metal layer forms a passivation layer, and wherein the method further comprises:
 forming an opening in the passivation layer to expose the second island in the second metal layer.   
     
     
         6 . The method of  claim 1 , wherein the second metal layer is separated from the first metal layer by a dielectric layer. 
     
     
         7 . The method of  claim 1 , wherein the first metal layer comprises at least one of copper (Cu), aluminum (Al), aluminum-silicon alloy, aluminum-copper alloy, or nickel (Ni), and wherein the second metal layer comprises at least one of copper (Cu), aluminum (Al), aluminum-silicon alloy, aluminum-copper alloy, or nickel (Ni). 
     
     
         8 . The method of  claim 1 , further comprising providing one or more bond pads that are in electrical contact with the second metal layer, the bond pads to transmit signals between the first semiconductor die and one or more external devices. 
     
     
         9 . The method of  claim 1 , further comprising providing an electrical pathway to transmit the power signal in the first semiconductor die from the second metal layer to the base metal layer via the island in the first metal layer. 
     
     
         10 . The method of  claim 1 , further comprising providing an electrical pathway to transmit the ground signal in the first semiconductor die from the first metal layer to a stacked die via the island in the second metal layer. 
     
     
         11 . The method of  claim 1 , further comprising:
 positioning the first semiconductor die on a lead frame of a package; and   stacking a second semiconductor die on top of the first semiconductor die.   
     
     
         12 . The method of  claim 1 , further comprising:
 forming a passivation layer over the second metal layer;   creating one or more openings in the passivation layer to expose contact points in the second metal layer;   stacking a second semiconductor die on the passivation layer; and   electrically coupling the second semiconductor die to the first semiconductor die via the one or more openings in the passivation layer.   
     
     
         13 . The method of  claim 12 , wherein the second semiconductor die is electrically coupled to the second metal layer through a solder bump. 
     
     
         14 . The method of  claim 12 , wherein the second semiconductor die is electrically coupled to the second metal layer through a copper pillar and a solder bump. 
     
     
         15 . The method of  claim 1 , wherein creating the second island in the second metal layer further comprises:
 creating the second island in the second metal layer to be aligned vertically with the first island in the first metal layer.   
     
     
         16 . The method of  claim 1 , wherein creating the first island in the first metal layer further comprises:
 creating the first island in a center location of the first metal layer.   
     
     
         17 . The method of  claim 1 , wherein:
 the first metal layer is a ground plane; and   the second metal layer is a power plane.   
     
     
         18 . A method of fabricating a chip, the method comprising:
 forming a base metal layer over a first semiconductor die;   forming a first metal layer that includes a plurality of islands individually surrounded along their entire periphery by a dielectric material, wherein the plurality of islands are to route at least one of (i) a ground signal or (ii) a power signal in the first semiconductor die, and wherein the first metal layer is electrically separate from the base metal layer;   forming an electrically insulating layer on the first metal layer; and   forming a second metal layer on the electrically insulating layer, wherein the second metal layer includes a plurality of islands individually surrounded along their entire periphery by a passivation material, wherein the plurality of islands are to route at least one of (i) a ground signal or (ii) a power signal in the first semiconductor die.   
     
     
         19 . The method of  claim 18 , wherein the electrically insulating layer comprises the dielectric material. 
     
     
         20 . The method of  claim 18 , further comprising:
 forming a passivation layer on the second metal layer, wherein the passivation layer comprises the passivation material that surrounds the islands of the second metal layer; and forming one or more openings in the passivation layer to expose at least one of the plurality of islands in the second metal layer.