Inventor · disambiguated record
Valeriy Sukharev
Also filed as: SUKHAREV VALERIY · SUKHAREV VALERIY K
22 granted patents·4 pending applications·1,007 citations·filing 1996–2016
96Inventor score
Top patents by PatentIndex Score
26 records- 0194US7138292B2Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbideLSI LOGIC CORP·Filed 2003·Granted Nov 21, 2006·76 cites·8 claims
- 0294US6087229AComposite semiconductor gate dielectricsLSI LOGIC CORP·Filed 1998·Granted Jul 11, 2000·180 cites·26 claims
- 0393US6114259AProcess for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damageLSI LOGIC CORP·Filed 1999·Granted Sep 5, 2000·218 cites·24 claims
- 0492US6303047B1Low dielectric constant multiple carbon-containing silicon oxide dielectric material for use in integrated circuit structures, and method of making sameLSI LOGIC CORP·Filed 1999·Granted Oct 16, 2001·81 cites·32 claims
- 0590US6033998AMethod of forming variable thickness gate dielectricsLSI LOGIC CORP·Filed 1998·Granted Mar 7, 2000·96 cites·22 claims
- 0689US5837598ADiffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making sameLSI LOGIC CORP·Filed 1997·Granted Nov 17, 1998·91 cites·15 claims
- 0788US5710079AMethod and apparatus for forming dielectric filmsLSI LOGIC CORP·Filed 1996·Granted Jan 20, 1998·83 cites·18 claims
- 0885US6365528B1Low temperature process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric-material characterized by improved resistance to oxidation and good gap-filling capabilitiesLSI LOGIC CORP·Filed 2000·Granted Apr 2, 2002·35 cites·20 claims
- 0979US6147012AProcess for forming low k silicon oxide dielectric material while suppressing pressure spiking and inhibiting increase in dielectric constantLSI LOGIC CORP·Filed 1999·Granted Nov 14, 2000·52 cites·20 claims
- 1073US7687303B1Method for determining via/contact pattern density effect in via/contact etch rateMENTOR GRAPHICS CORP·Filed 2005·Granted Mar 30, 2010·6 cites·12 claims
- 1172US6506678B1Integrated circuit structures having low k porous aluminum oxide dielectric material separating aluminum lines, and method of making sameLSI LOGIC CORP·Filed 2000·Granted Jan 14, 2003·15 cites·7 claims
- 1272US6030460AMethod and apparatus for forming dielectric filmsLSI LOGIC CORP·Filed 1997·Granted Feb 29, 2000·35 cites·16 claims
- 1367US9135391B2Determination of electromigration susceptibility based on hydrostatic stress analysisMENTOR GRAPHICS CORP·Filed 2013·Granted Sep 15, 2015·2 cites·18 claims
- 1461US6524974B1Formation of improved low dielectric constant carbon-containing silicon oxide dielectric material by reaction of carbon-containing silane with oxidizing agent in the presence of one or more reaction retardantsLSI LOGIC CORP·Filed 1999·Granted Feb 25, 2003·26 cites·10 claims
- 1559US6777807B1Interconnect integrationLSI LOGIC CORP·Filed 2003·Granted Aug 17, 2004·7 cites·15 claims
- 1655US9740804B2Chip-scale electrothermal analysisMENTOR GRAPHICS CORP·Filed 2015·Granted Aug 22, 2017·1 cites·12 claims
- 1753US7408227B2Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbideLSI CORP·Filed 2006·Granted Aug 5, 2008·0 cites·9 claims
- 1847US10013523B2Full-chip assessment of time-dependent dielectric breakdownMENTOR GRAPHICS CORP·Filed 2016·Granted Jul 3, 2018·0 cites·18 claims
- 1940US2004238960A1Interconnect integrationLSI LOGIC CORP·Filed 2004·Application pending·0 cites
- 2040US2006290694A1Local reconstruction of a tetrahedral gridLSI LOGIC CORP·Filed 2005·Application pending·0 cites
- 2137US6935933B1Viscous electropolishing systemLSI LOGIC CORP·Filed 2001·Granted Aug 30, 2005·0 cites·17 claims
- 2236US9836569B2Leakage reduction using stress-enhancing filler cellsMENTOR GRAPHICS CORP·Filed 2016·Granted Dec 5, 2017·0 cites·17 claims
- 2336US2004111244A1Algorithm for fast determination of suspicious cites inside interconnect segments with the high probability of nucleation electromigration-induced voidsFiled 2002·Application pending·0 cites
- 2435US6426286B1Interconnection system with lateral barrier layerLSI LOGIC CORP·Filed 2000·Granted Jul 30, 2002·0 cites·8 claims
- 2534US6759337B1Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrateLSI LOGIC CORP·Filed 1999·Granted Jul 6, 2004·3 cites·17 claims
- 2631US2005006770A1Copper-low-K dual damascene interconnect with improved reliabilityFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →