Inventor · disambiguated record
Shawn A. Adderly
Also filed as: ADDERLY SHAWN A
15 granted patents·26 citations·filing 2013–2018
89Inventor score
Top patents by PatentIndex Score
15 records- 0184US10078183B2Waveguide structures used in phonotics chip packagingGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 18, 2018·5 cites·20 claims
- 0284US9583401B2Nano deposition and ablation for the repair and fabrication of integrated circuitsIBM·Filed 2014·Granted Feb 28, 2017·2 cites·10 claims
- 0382US10224225B2Centering substrates on a chuckIBM·Filed 2018·Granted Mar 5, 2019·2 cites·20 claims
- 0480US9997385B2Centering substrates on a chuckIBM·Filed 2017·Granted Jun 12, 2018·2 cites·19 claims
- 0579US9685362B2Apparatus and method for centering substrates on a chuckIBM·Filed 2014·Granted Jun 20, 2017·3 cites·24 claims
- 0679US9543219B2Void monitoring device for measurement of wafer temperature variationsGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 10, 2017·4 cites·17 claims
- 0776US9508578B2Method and apparatus for detecting foreign material on a chuckGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 29, 2016·3 cites·18 claims
- 0871US9275868B2Uniform roughness on backside of a waferIBM·Filed 2013·Granted Mar 1, 2016·2 cites·20 claims
- 0968US9087839B2Semiconductor structures with metal linesIBM·Filed 2013·Granted Jul 21, 2015·2 cites·20 claims
- 1062US9330988B1Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughnessIBM·Filed 2014·Granted May 3, 2016·1 cites·15 claims
- 1155US10607899B2Nano deposition and ablation for the repair and fabrication of integrated circuitsIBM·Filed 2017·Granted Mar 31, 2020·0 cites·5 claims
- 1250US9006703B2Method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereofIBM·Filed 2013·Granted Apr 14, 2015·0 cites·12 claims
- 1349US9196519B2Achieving uniform capacitance between an electrostatic chuck and a semiconductor waferIBM·Filed 2013·Granted Nov 24, 2015·0 cites·20 claims
- 1447US9576863B2Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughnessIBM·Filed 2015·Granted Feb 21, 2017·0 cites·20 claims
- 1545US9201806B2Anticipatorily loading a page of memoryIBM·Filed 2013·Granted Dec 1, 2015·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →