Inventor · disambiguated record
Daniel S. Vanslette
Also filed as: VANSLETTE DANIEL S · VANSLETTE DANIEL SCOTT
23 granted patents·4 pending applications·91 citations·filing 1998–2018
93Inventor score
Top patents by PatentIndex Score
27 records- 0195US8791016B2Through silicon via wafer, contacts and design structuresIBM·Filed 2012·Granted Jul 29, 2014·20 cites·20 claims
- 0291US8021943B2Simultaneously formed isolation trench and through-box contact for silicon-on-insulator technologyIBM·Filed 2009·Granted Sep 20, 2011·22 cites·18 claims
- 0388US8299615B2Methods and structures for controlling wafer curvatureFAYAZ MOHAMMED FAZIL·Filed 2009·Granted Oct 30, 2012·19 cites·32 claims
- 0486US10147839B2Method of forming a metal silicide transparent conductive electrodeIBM·Filed 2015·Granted Dec 4, 2018·2 cites·10 claims
- 0585US9312426B2Structure with a metal silicide transparent conductive electrode and a method of forming the structureGAMBINO JEFFREY P·Filed 2011·Granted Apr 12, 2016·3 cites·15 claims
- 0671US8918988B2Methods for controlling wafer curvatureFAYAZ MOHAMMED FAZIL·Filed 2012·Granted Dec 30, 2014·3 cites·15 claims
- 0768US11195969B2Method of forming a metal silicide transparent conductive electrodeIBM·Filed 2018·Granted Dec 7, 2021·0 cites·12 claims
- 0868US11056610B2Method of forming a metal silicide transparent conductive electrodeIBM·Filed 2018·Granted Jul 6, 2021·0 cites·15 claims
- 0968US8003536B2Electromigration resistant aluminum-based metal interconnect structureIBM·Filed 2009·Granted Aug 23, 2011·2 cites·7 claims
- 1067US9455214B2Wafer frontside-backside through silicon viaIBM·Filed 2014·Granted Sep 27, 2016·2 cites·20 claims
- 1161US8188591B2Integrated structures of high performance active devices and passive devicesRASSEL ROBERT M·Filed 2010·Granted May 29, 2012·1 cites·20 claims
- 1259US8084864B2Electromigration resistant aluminum-based metal interconnect structureCHAPPLE-SOKOL JONATHAN D·Filed 2011·Granted Dec 27, 2011·1 cites·13 claims
- 1357US6762121B2Method of forming refractory metal contact in an opening, and resulting structureIBM·Filed 2001·Granted Jul 13, 2004·2 cites·16 claims
- 1456US9245850B2Through silicon via wafer, contacts and design structuresIBM·Filed 2014·Granted Jan 26, 2016·0 cites·19 claims
- 1551US6245668B1Sputtered tungsten diffusion barrier for improved interconnect robustnessIBM·Filed 1998·Granted Jun 12, 2001·14 cites·22 claims
- 1650US8232139B1Integrated structures of high performance active devices and passive devicesRASSEL ROBERT M·Filed 2012·Granted Jul 31, 2012·0 cites·19 claims
- 1747US9041210B2Through silicon via wafer and methods of manufacturingGAMBINO JEFFREY P·Filed 2012·Granted May 26, 2015·0 cites·11 claims
- 1845US2009230555A1Tungsten liner for aluminum-based electromigration resistant interconnect structureIBM·Filed 2008·Application pending·0 cites
- 1943US9390969B2Integrated circuit and interconnect, and method of fabricating sameGLOBALFOUNDRIES INC·Filed 2015·Granted Jul 12, 2016·0 cites·18 claims
- 2042US9443764B2Method of eliminating poor reveal of through silicon viasGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 13, 2016·0 cites·19 claims
- 2142US8809998B2Semiconductor device including in wafer inductors, related method and design structureCAMILLO-CASTILLO RENATA A·Filed 2011·Granted Aug 19, 2014·0 cites·19 claims
- 2240US6838364B2Sputtered tungsten diffusion barrier for improved interconnect robustnessIBM·Filed 2001·Granted Jan 4, 2005·0 cites·17 claims
- 2339US6900505B2Method of forming refractory metal contact in an opening, and resulting structureIBM·Filed 2004·Granted May 31, 2005·0 cites·20 claims
- 2436US2012086101A1Integrated circuit and interconnect, and method of fabricating sameDEMUYNCK DAVID A·Filed 2010·Application pending·0 cites
- 2535US2002175413A1Method for utilizing tungsten barrier in contacts to silicide and structure produced therbyIBM·Filed 2001·Application pending·0 cites
- 2634US2017069518A1Electrostatic substrate holder with non-planar surface and method of etchingGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 2725US9406562B2Integrated circuit and design structure having reduced through silicon via-induced stressBONN JEFFREY P·Filed 2011·Granted Aug 2, 2016·0 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →