Inventor · disambiguated record
Nicholas V. Licausi
Also filed as: LICAUSI NICHOLAS · LICAUSI NICHOLAS V · LICAUSI NICHOLAS VINCENT
54 granted patents·9 pending applications·594 citations·filing 2011–2023
98Inventor score
Files withGLOBALFOUNDRIES INC47GLOBALFOUNDRIES US INC6LICAUSI NICHOLAS2LICAUSI NICHOLAS V2MASZARA WITOLD P2
Top patents by PatentIndex Score
63 records- 0198US10177028B1Method for manufacturing fully aligned via structures having relaxed gapfillsGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 8, 2019·44 cites·20 claims
- 0298US8846491B1Forming a diffusion break during a RMG processGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 30, 2014·97 cites·20 claims
- 0397US10475692B2Self aligned buried power railGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 12, 2019·14 cites·18 claims
- 0497US10304833B1Method of forming complementary nano-sheet/wire transistor devices with same depth contactsGLOBALFOUNDRIES INC·Filed 2018·Granted May 28, 2019·19 cites·20 claims
- 0597US10002786B1Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cutsGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 19, 2018·20 cites·18 claims
- 0697US8691640B1Methods of forming dielectrically isolated fins for a FinFET semiconductor by performing an etching process wherein the etch rate is modified via inclusion of a dopant materialGLOBALFOUNDRIES INC·Filed 2013·Granted Apr 8, 2014·33 cites·19 claims
- 0796US9812351B1Interconnection cells having variable width metal lines and fully-self aligned continuity cutsGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 7, 2017·18 cites·20 claims
- 0896US9553194B1Method for improved fin profileGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 24, 2017·19 cites·16 claims
- 0995US10043703B2Apparatus and method for forming interconnection lines having variable pitch and variable widthsGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 7, 2018·10 cites·8 claims
- 1095US8481410B1Methods of epitaxial FinFETLICAUSI NICHOLAS·Filed 2012·Granted Jul 9, 2013·40 cites·20 claims
- 1195US8476137B1Methods of FinFET height controlLICAUSI NICHOLAS·Filed 2012·Granted Jul 2, 2013·40 cites·23 claims
- 1294US9691775B1Combined SADP fins for semiconductor devices and methods of making the sameGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 27, 2017·25 cites·12 claims
- 1394US8673718B2Methods of forming FinFET devices with alternative channel materialsMASZARA WITOLD P·Filed 2012·Granted Mar 18, 2014·27 cites·16 claims
- 1494US8669186B2Methods of forming SRAM devices using sidewall image transfer techniquesLICAUSI NICHOLAS V·Filed 2012·Granted Mar 11, 2014·26 cites·20 claims
- 1594US8557675B2Methods of patterning features in a structure using multiple sidewall image transfer techniqueLICAUSI NICHOLAS V·Filed 2011·Granted Oct 15, 2013·24 cites·22 claims
- 1693US9887127B1Interconnection lines having variable widths and partially self-aligned continuity cutsGLOBALFOUNDRIES INC·Filed 2016·Granted Feb 6, 2018·8 cites·8 claims
- 1793US9508712B2Semiconductor device with a multiple nanowire channel structure and methods of variably connecting such nanowires for current density modulationGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 29, 2016·17 cites·18 claims
- 1892US9318388B2Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 19, 2016·9 cites·18 claims
- 1992US8580642B1Methods of forming FinFET devices with alternative channel materialsMASZARA WITOLD P·Filed 2012·Granted Nov 12, 2013·19 cites·21 claims
- 2090US10134580B1Metallization levels and methods of making thereofGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 20, 2018·6 cites·17 claims
- 2190US10109526B1Etch profile control during skip via formationGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 23, 2018·9 cites·18 claims
- 2290US9093302B2Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2013·Granted Jul 28, 2015·10 cites·14 claims
- 2390US8815685B2Methods for fabricating integrated circuits having confined epitaxial growth regionsGLOBALFOUNDRIES INC·Filed 2013·Granted Aug 26, 2014·10 cites·18 claims
- 2489US10083858B2Interconnection lines having variable widths and partially self-aligned continuity cutsGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 25, 2018·5 cites·11 claims
- 2588US9530654B2FINFET fin height controlGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 27, 2016·8 cites·12 claims
- 2683US10163633B2Non-mandrel cut formationGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 25, 2018·3 cites·19 claims
- 2782US10770392B1Line end structures for semiconductor devicesGLOBALFOUNDRIES INC·Filed 2019·Granted Sep 8, 2020·3 cites·20 claims
- 2882US10707119B1Interconnect structures with airgaps and dielectric-capped interconnectsGLOBALFOUNDRIES INC·Filed 2019·Granted Jul 7, 2020·3 cites·14 claims
- 2982US10580696B1Interconnects formed by a metal displacement reactionGLOBALFOUNDRIES INC·Filed 2018·Granted Mar 3, 2020·3 cites·20 claims
- 3082US8932934B2Methods of self-forming barrier integration with pore stuffed ULK materialGLOBALFOUNDRIES INC·Filed 2013·Granted Jan 13, 2015·6 cites·13 claims
- 3181US10818494B2Metal on metal multiple patterningGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 27, 2020·2 cites·20 claims
- 3280US10978388B2Skip via for metal interconnectsIBM·Filed 2018·Granted Apr 13, 2021·3 cites·7 claims
- 3380US10366919B2Fully aligned via in ground rule regionGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 30, 2019·2 cites·18 claims
- 3477US11121087B2Methods of forming a conductive contact structure to an embedded memory device on an IC product and a corresponding IC productGLOBALFOUNDRIES US INC·Filed 2019·Granted Sep 14, 2021·2 cites·20 claims
- 3576US9054052B2Methods for integration of pore stuffing materialGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 9, 2015·3 cites·17 claims
- 3675US12142516B2Self aligned buried power railGLOBALFOUNDRIES US INC·Filed 2022·Granted Nov 12, 2024·0 cites·20 claims
- 3774US10485111B2Via and skip via structuresGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 19, 2019·2 cites·16 claims
- 3874US10211100B2Methods of forming an air gap adjacent a gate of a transistor and a gate contact above the active region of the transistorGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 19, 2019·2 cites·20 claims
- 3970US10677855B2Structure, method and system for measuring RIE lag depthGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 9, 2020·1 cites·9 claims
- 4069US12498402B2Method and structure to incorporate multiple low loss photonic circuit componentsPSIQUANTUM CORP·Filed 2021·Granted Dec 16, 2025·0 cites·19 claims
- 4169US10199261B1Via and skip via structuresGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 5, 2019·1 cites·20 claims
- 4267US11398378B2Metal on metal multiple patterningGLOBALFOUNDRIES INC·Filed 2020·Granted Jul 26, 2022·0 cites·20 claims
- 4364US9570394B1Formation of IC structure with pair of unitary metal finsGLOBALFOUNDRIES INC·Filed 2016·Granted Feb 14, 2017·1 cites·20 claims
- 4463US11309210B2Self aligned buried power railGLOBALFOUNDRIES US INC·Filed 2019·Granted Apr 19, 2022·0 cites·20 claims
- 4562US11114338B2Fully aligned via in ground rule regionGLOBALFOUNDRIES US INC·Filed 2019·Granted Sep 7, 2021·0 cites·14 claims
- 4652US2025208446A1Bto phase shifter and method of fabrication thereofPSIQUANTUM CORP·Filed 2023·Application pending·0 cites
- 4750US10283372B2Interconnects formed by a metal replacement processGLOBALFOUNDRIES INC·Filed 2017·Granted May 7, 2019·0 cites·20 claims
- 4850US2016190306A1Finfet device with a substantially self-aligned isolation region positioned under the channel regionGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 4948US11101169B2Interconnect structures with airgaps arranged between capped interconnectsGLOBALFOUNDRIES US INC·Filed 2019·Granted Aug 24, 2021·0 cites·20 claims
- 5048US10832944B2Interconnect structure having reduced resistance variation and method of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Nov 10, 2020·0 cites·18 claims
Showing the top 50 of 63 patent records by PatentIndex Score.
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