Finfet device with a substantially self-aligned isolation region positioned under the channel region

Abstract

One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device.

What is claimed: 
     
         1 . A FinFET device comprising a channel region and a plurality of source/drain regions, said device having a gate-length direction that corresponds to a direction of current travel when said device is operational, the device comprising:
 a semiconductor substrate;   a fin structure that is positioned vertically above said substrate, said fin structure being comprised of a first semiconductor material;   a gate structure positioned around a portion of said fin structure in said channel region of said device, said fin structure extending in said gate-length direction across said channel region and said source/drain regions for said device;   spaced-apart portions of a second semiconductor material positioned vertically between said fin structure and said substrate, said second semiconductor material being a different semiconductor material than said first semiconductor material; and   a local channel isolation material positioned laterally between said spaced-apart portions of said second semiconductor material and vertically below said fin structure and said gate structure, said local channel isolation material being positioned under at least a portion of said channel region of said device.   
     
     
         2 . The device of  claim 1 , wherein said semiconductor substrate and said first semiconductor material are silicon and said second semiconductor material is silicon/germanium (Si x Ge 1-x ). 
     
     
         3 . The device of  claim 1 , wherein said semiconductor substrate and said first semiconductor material are comprised of the same material. 
     
     
         4 . The device of  claim 1 , wherein said gate structure comprises a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal. 
     
     
         5 . The device of  claim 1 , wherein said local channel isolation material abuts each of said spaced-apart portions of said second semiconductor material. 
     
     
         6 . The device of  claim 1 , wherein said second semiconductor material is positioned under said fin structure in said source/drain regions of said device. 
     
     
         7 . The device of  claim 1 , wherein a lateral width of said local channel isolation material in said gate length direction is greater than a lateral width of said gate structure at an upper surface of said fin structure. 
     
     
         8 . A FinFET device comprising a channel region and a plurality of source/drain regions, said device having a gate-length direction that corresponds to a direction of current travel when said device is operational, said device comprising:
 a semiconductor substrate;   a fin structure that is positioned vertically above said substrate, said fin structure being comprised of a first semiconductor material;   a gate structure positioned around a portion of said fin structure in said channel region of said device, said fin structure extending in said gate-length direction across said channel region and said source/drain regions for said device;   spaced-apart portions of a second semiconductor material positioned vertically between said fin structure and said substrate, said second semiconductor material being a different semiconductor material than said first semiconductor material; and   a local channel isolation material positioned laterally between said spaced-apart portions of said second semiconductor material and vertically below said fin structure and said gate structure, wherein a lateral width of said local channel isolation material in said gate length direction is greater than a lateral width of said gate structure at an upper surface of said fin structure and wherein said local channel isolation material abuts each of said spaced-apart portions of said second semiconductor material.   
     
     
         9 . The device of  claim 8 , wherein said semiconductor substrate and said first semiconductor material are comprised of the same material. 
     
     
         10 . The device of  claim 8 , wherein said gate structure comprises a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal. 
     
     
         11 . The device of  claim 8 , wherein said second semiconductor material is positioned under said fin structure in said source/drain regions of said device. 
     
     
         12 . A FinFET device comprising a channel region and a plurality of source/drain regions, said device having a gate-length direction that corresponds to a direction of current travel when said device is operational, said device comprising:
 a semiconductor substrate;   a fin structure that is positioned vertically above said substrate, said fin structure being comprised of a first semiconductor material, wherein said semiconductor substrate and said first semiconductor material are comprised of the same material;   a gate structure positioned around a portion of said fin structure in said channel region of said device, said fin structure extending in said gate-length direction across said channel region and said source/drain regions for said device;   spaced-apart portions of a second semiconductor material positioned vertically between said fin structure and said substrate in said source/drain regions, said second semiconductor material being a different semiconductor material than said first semiconductor material; and   a local channel isolation material positioned laterally between said spaced-apart portions of said second semiconductor material and vertically below said fin structure and said gate structure, wherein a lateral width of said local channel isolation material in said gate length direction is greater than a lateral width of said gate structure at an upper surface of said fin structure.   
     
     
         13 . The device of  claim 12 , wherein said gate structure comprises a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal. 
     
     
         14 . The device of  claim 12 , wherein said local channel isolation material abuts each of said spaced-apart portions of said second semiconductor material.