Inventor · disambiguated record
Alexander Tetelbaum
Also filed as: TETELBAUM ALEXANDER · TETELBAUM ALEXANDER Y
51 granted patents·5 pending applications·626 citations·filing 2000–2015
98Inventor score
Files withLSI LOGIC CORP32TETELBAUM ALEXANDER12LSI CORP6TETELBAUM ALEXANDER Y3SANDISK TECHNOLOGIES INC2
Top patents by PatentIndex Score
56 records- 0194US8539424B2System and method for designing integrated circuits that employ adaptive voltage scaling optimizationTETELBAUM ALEXANDER·Filed 2008·Granted Sep 17, 2013·43 cites·15 claims
- 0291US6594805B1Integrated design system and method for reducing and avoiding crosstalkLSI LOGIC CORP·Filed 2001·Granted Jul 15, 2003·73 cites·29 claims
- 0388US8645888B2Circuit timing analysis incorporating the effects of temperature inversionTETELBAUM ALEXANDER·Filed 2012·Granted Feb 4, 2014·9 cites·8 claims
- 0487US7480881B2Method and computer program for static timing analysis with delay de-rating and clock conservatism reductionLSI LOGIC CORP·Filed 2006·Granted Jan 20, 2009·26 cites·34 claims
- 0586US6532572B1Method for estimating porosity of hardmacsLSI LOGIC CORP·Filed 2001·Granted Mar 11, 2003·45 cites·27 claims
- 0683US8181144B2Circuit timing analysis incorporating the effects of temperature inversionTETELBAUM ALEXANDER·Filed 2008·Granted May 15, 2012·10 cites·13 claims
- 0783US6611951B1Method for estimating cell porosity of hardmacsLSI LOGIC CORP·Filed 2001·Granted Aug 26, 2003·49 cites·30 claims
- 0882US7039891B2Method of clock driven cell placement and clock tree synthesis for integrated circuit designLSI LOGIC CORP·Filed 2003·Granted May 2, 2006·32 cites·18 claims
- 0981US9397648B1Systems, circuitry, and methods for decoding pulse width modulated signalSANDISK TECHNOLOGIES INC·Filed 2015·Granted Jul 19, 2016·5 cites·20 claims
- 1080US6907590B1Integrated circuit design system and method for reducing and avoiding crosstalkLSI LOGIC CORP·Filed 2001·Granted Jun 14, 2005·31 cites·34 claims
- 1179US8799839B1Extraction tool and method for determining maximum and minimum stage delays associated with integrated circuit interconnectsTETELBAUM ALEXANDER Y·Filed 2008·Granted Aug 5, 2014·14 cites·20 claims
- 1278US7971169B1System and method for reducing the generation of inconsequential violations resulting from timing analysesLSI CORP·Filed 2008·Granted Jun 28, 2011·10 cites·20 claims
- 1377US8010935B2Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuitLSI CORP·Filed 2008·Granted Aug 30, 2011·4 cites·20 claims
- 1477US6502222B1Method of clock buffer partitioning to minimize clock skew for an integrated circuit designLSI LOGIC CORP·Filed 2001·Granted Dec 31, 2002·25 cites·9 claims
- 1576US8397196B2Intelligent dummy metal fill process for integrated circuitsTETELBAUM ALEXANDER·Filed 2011·Granted Mar 12, 2013·4 cites·20 claims
- 1676US7062737B2Method of automated repair of crosstalk violations and timing violations in an integrated circuit designLSI LOGIC CORP·Filed 2004·Granted Jun 13, 2006·23 cites·22 claims
- 1774US7370309B2Method and computer program for detailed routing of an integrated circuit design with multiple routing rules and net constraintsLSI LOGIC CORP·Filed 2005·Granted May 6, 2008·6 cites·16 claims
- 1873US7178121B2Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit designLSI LOGIC CORP·Filed 2005·Granted Feb 13, 2007·6 cites·28 claims
- 1971US8225257B2Reducing path delay sensitivity to temperature variation in timing-critical pathsTETELBAUM ALEXANDER·Filed 2008·Granted Jul 17, 2012·5 cites·20 claims
- 2071US8191029B2Timing error sampling generator, critical path monitor for hold and setup violations of an integrated circuit and a method of timing testingTETELBAUM ALEXANDER·Filed 2008·Granted May 29, 2012·4 cites·16 claims
- 2171US7107558B2Method of finding critical nets in an integrated circuit designLSI LOGIC CORP·Filed 2004·Granted Sep 12, 2006·16 cites·22 claims
- 2271US6810505B2Integrated circuit design flow with capacitive marginLSI LOGIC CORP·Filed 2002·Granted Oct 26, 2004·18 cites·11 claims
- 2369US6907586B1Integrated design system and method for reducing and avoiding crosstalkLSI LOGIC CORP·Filed 2001·Granted Jun 14, 2005·15 cites·29 claims
- 2468US8516424B2Timing signoff system and method that takes static and dynamic voltage drop into accountTETELBAUM ALEXANDER·Filed 2011·Granted Aug 20, 2013·3 cites·20 claims
- 2568US7739639B2Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layerLSI CORP·Filed 2006·Granted Jun 15, 2010·3 cites·15 claims
- 2668US7043708B2Intelligent crosstalk delay estimator for integrated circuit design flowLSI LOGIC CORP·Filed 2003·Granted May 9, 2006·13 cites·14 claims
- 2768US6880141B1Wire delay distributed modelLSI LOGIC CORP·Filed 2001·Granted Apr 12, 2005·13 cites·14 claims
- 2867US6609238B1Method of control cell placement to minimize connection length and cell delayLSI LOGIC CORP·Filed 2001·Granted Aug 19, 2003·12 cites·19 claims
- 2966US8694937B2Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the sameLSI CORP·Filed 2012·Granted Apr 8, 2014·2 cites·14 claims
- 3066US6594807B1Method for minimizing clock skew for an integrated circuitLSI LOGIC CORP·Filed 2001·Granted Jul 15, 2003·13 cites·7 claims
- 3164US6507937B1Method of global placement of control cells and hardmac pins in a datapath macro for an integrated circuit designLSI LOGIC CORP·Filed 2001·Granted Jan 14, 2003·10 cites·6 claims
- 3262US7015569B1Method and apparatus for implementing a co-axial wire in a semiconductor chipLSI LOGIC CORP·Filed 2004·Granted Mar 21, 2006·10 cites·16 claims
- 3362US6543038B1Elmore model enhancementLSI LOGIC CORP·Filed 2001·Granted Apr 1, 2003·8 cites·16 claims
- 3462US6480994B1Balanced clock placement for integrated circuits containing megacellsLSI LOGIC CORP·Filed 2001·Granted Nov 12, 2002·9 cites·6 claims
- 3562US6442737B1Method of generating an optimal clock buffer set for minimizing clock skew in balanced clock treesLSI LOGIC CORP·Filed 2001·Granted Aug 27, 2002·9 cites·8 claims
- 3661US7062731B2Method of noise analysis and correction of noise violations for an integrated circuit designLSI LOGIC CORP·Filed 2003·Granted Jun 13, 2006·7 cites·27 claims
- 3761US6948142B2Intelligent engine for protection against injected crosstalk delayLSI LOGIC CORP·Filed 2003·Granted Sep 20, 2005·8 cites·18 claims
- 3860US7076406B1Minimal bends connection models for wire density calculationLSI LOGIC CORP·Filed 2001·Granted Jul 11, 2006·7 cites·14 claims
- 3959US6725389B1Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limitLSI LOGIC CORP·Filed 2000·Granted Apr 20, 2004·7 cites·7 claims
- 4057US8922176B2Programmable slew rate power switchTETELBAUM ALEXANDER·Filed 2012·Granted Dec 30, 2014·1 cites·21 claims
- 4157US6588003B1Method of control cell placement for datapath macros in integrated circuit designsLSI LOGIC CORP·Filed 2001·Granted Jul 1, 2003·5 cites·8 claims
- 4255US2014089881A1Circuit Timing Analysis Incorporating the Effects of Temperature InversionLSI CORP·Filed 2013·Application pending·0 cites
- 4354US7174524B2Method of floorplanning and cell placement for integrated circuit chip architecture with internal I/O ringLSI LOGIC CORP·Filed 2004·Granted Feb 6, 2007·3 cites·14 claims
- 4453US8775995B2Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layerLSI CORP·Filed 2012·Granted Jul 8, 2014·0 cites·6 claims
- 4552US7213223B2Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatismLSI LOGIC CORP·Filed 2004·Granted May 1, 2007·2 cites·12 claims
- 4651US8473890B2Timing error sampling generator and a method of timing testingTETELBAUM ALEXANDER·Filed 2012·Granted Jun 25, 2013·0 cites·14 claims
- 4751US6842042B2Global chip interconnectLSI LOGIC CORP·Filed 2002·Granted Jan 11, 2005·4 cites·18 claims
- 4849US6449760B1Pin placement method for integrated circuitsLSI LOGIC CORP·Filed 2000·Granted Sep 10, 2002·4 cites·4 claims
- 4949US2013080198A1Timing signoff for maximum profitTETELBAUM ALEXANDER Y·Filed 2011·Application pending·0 cites
- 5045US8332792B2Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the sameTETELBAUM ALEXANDER·Filed 2010·Granted Dec 11, 2012·0 cites·16 claims
Showing the top 50 of 56 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →