Circuit Timing Analysis Incorporating the Effects of Temperature Inversion

Abstract

Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second temperatures; performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner.

What is claimed is: 
     
         1 . A method for increasing an accuracy of timing characterization of a circuit including at least one cell in a cell library, the method comprising the steps of:
 performing cell library timing characterization for the at least one cell in the circuit for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively;   selecting one or more additional temperatures between the first and second temperatures;   performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and   performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner.   
     
     
         2 . The method of  claim 1 , wherein the step of performing cell timing characterization comprises simulating delay values for the at least one cell at each of the PVT corners in the cell library using at least one of a static timing analysis tool and a statistical static timing analysis tool. 
     
     
         3 . The method of  claim 1 , wherein the step of performing cell timing characterization comprises determining all critical timing paths in the circuit. 
     
     
         4 . The method of  claim 3 , wherein the step of determining all timing critical paths in the circuit comprises identifying any signal path having a length that is greater than a prescribed threshold length, based at least in part on a physical layout of the circuit. 
     
     
         5 . The method of  claim 3 , wherein the step of determining all timing critical paths in the circuit comprises identifying any signal path in the circuit having a timing slack less than a prescribed threshold value. 
     
     
         6 . A method for increasing an accuracy of timing characterization of a circuit including at least one cell in a cell library, the method comprising the steps of:
 for each cell in the circuit, determining a first temperature at which cell delay is minimum;   for each cell in the circuit, determining a second temperature at which cell delay is maximum;   for each cell in the circuit, storing the first temperature and a first cell delay value corresponding thereto, and storing the second temperature and a second cell delay value corresponding thereto, the first and second cell delay values for each cell being stored in the cell library as new tables; and   replacing one or more delay values stored in current delay tables in the cell library, used by a delay calculator in performing timing characterization of the circuit, by one or more corresponding delay values stored in the new tables.   
     
     
         7 . A method for increasing an accuracy of timing characterization of a circuit including at least one cell in a cell library, the method comprising the steps of:
 determining all timing critical paths in the circuit;   generating a set of circuit simulation functional parameters for all timing critical paths in the circuit;   performing circuit simulation at least on each of the timing critical paths using the set of circuit simulation functional parameters by sweeping a temperature at which the circuit simulation is performed within a prescribed range of each process, voltage and temperature (PVT) corner in the cell library, the circuit simulation generating respective path delays for each of the critical timing paths in the circuit; and   determining timing margins to be used in increasing the accuracy of the timing characterization of the circuit.   
     
     
         8 . The method of  claim 7 , wherein the step of determining all timing critical paths in the circuit comprises identifying any signal path in the circuit having a timing slack less than a prescribed threshold value. 
     
     
         9 . The method of  claim 7 , wherein the step of determining all timing critical paths in the circuit comprises identifying any signal path having a length that is greater than a prescribed threshold length, based at least in part on a physical layout of the circuit.