Inventor · disambiguated record
Heejo Chi
Also filed as: CHI HEEJO
85 granted patents·14 pending applications·1,342 citations·filing 2007–2022
99Inventor score
Top patents by PatentIndex Score
99 records- 0199US7928552B1Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2010·Granted Apr 19, 2011·110 cites·10 claims
- 0298US9735113B2Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSPCHI HEEJO·Filed 2010·Granted Aug 15, 2017·60 cites·6 claims
- 0398US9362161B2Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor packageSTATS CHIPPAC LTD·Filed 2014·Granted Jun 7, 2016·47 cites·23 claims
- 0498US8288209B1Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor dieCHI HEEJO·Filed 2011·Granted Oct 16, 2012·52 cites·20 claims
- 0598US8264091B2Integrated circuit packaging system with encapsulated via and method of manufacture thereofCHO NAMJU·Filed 2009·Granted Sep 11, 2012·95 cites·20 claims
- 0698US8143097B2Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMPCHI HEEJO·Filed 2009·Granted Mar 27, 2012·80 cites·20 claims
- 0798US8138014B2Method of forming thin profile WLCSP with vertical interconnect over package footprintCHI HEEJO·Filed 2010·Granted Mar 20, 2012·42 cites·20 claims
- 0897US9496152B2Carrier system with multi-tier conductive posts and method of manufacture thereofCHO NAMJU·Filed 2010·Granted Nov 15, 2016·42 cites·20 claims
- 0997US9048306B2Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMPCHI HEEJO·Filed 2012·Granted Jun 2, 2015·27 cites·8 claims
- 1097US8318539B2Method of manufacture of integrated circuit packaging system with multi-tier conductive interconnectsCHO NAMJU·Filed 2011·Granted Nov 27, 2012·37 cites·10 claims
- 1196US9397050B2Semiconductor device and method of forming pre-molded semiconductor die having bumps embedded in encapsulantSHIN HANGIL·Filed 2009·Granted Jul 19, 2016·53 cites·17 claims
- 1296US8390108B2Integrated circuit packaging system with stacking interconnect and method of manufacture thereofCHO NAMJU·Filed 2009·Granted Mar 5, 2013·47 cites·19 claims
- 1396US8039316B2Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2009·Granted Oct 18, 2011·46 cites·20 claims
- 1495US10510703B2Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor packageSTATS CHIPPAC PTE LTD·Filed 2017·Granted Dec 17, 2019·8 cites·25 claims
- 1595US9875911B2Semiconductor device and method of forming interposer with opening to contain semiconductor diePAGAILA REZA A·Filed 2010·Granted Jan 23, 2018·19 cites·11 claims
- 1695US8471394B2Integrated circuit packaging system with package-on-package and method of manufacture thereofJANG KI YOUN·Filed 2011·Granted Jun 25, 2013·22 cites·9 claims
- 1795US8384227B2Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor dieSTATS CHIPPAC LTD·Filed 2010·Granted Feb 26, 2013·17 cites·25 claims
- 1895US8349658B2Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframeSTATS CHIPPAC LTD·Filed 2010·Granted Jan 8, 2013·19 cites·25 claims
- 1995US8202797B2Integrated circuit system with recessed through silicon via pads and method of manufacture thereofCHI HEEJO·Filed 2010·Granted Jun 19, 2012·20 cites·20 claims
- 2095US7863735B1Integrated circuit packaging system with a tiered substrate package and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2009·Granted Jan 4, 2011·38 cites·20 claims
- 2194US8716065B2Integrated circuit packaging system with encapsulation and method of manufacture thereofCHI HEEJO·Filed 2011·Granted May 6, 2014·17 cites·20 claims
- 2294US8409917B2Integrated circuit packaging system with an interposer substrate and method of manufacture thereofYOON IN SANG·Filed 2011·Granted Apr 2, 2013·19 cites·20 claims
- 2394US8357564B2Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor dieSTATS CHIPPAC LTD·Filed 2010·Granted Jan 22, 2013·21 cites·25 claims
- 2494US8106498B2Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereofSHIN HANGIL·Filed 2009·Granted Jan 31, 2012·38 cites·20 claims
- 2592US9330994B2Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuringSTATS CHIPPAC LTD·Filed 2014·Granted May 3, 2016·22 cites·21 claims
- 2692US9331003B1Integrated circuit packaging system with pre-molded leadframe and method of manufacture thereofCAMACHO ZIGMUND RAMIREZ·Filed 2014·Granted May 3, 2016·15 cites·19 claims
- 2792US9269595B2Semiconductor device with thin profile WLCSP with vertical interconnect over package footprintCHI HEEJO·Filed 2012·Granted Feb 23, 2016·11 cites·24 claims
- 2892US8035235B2Integrated circuit packaging system with package-on-package and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2009·Granted Oct 11, 2011·21 cites·17 claims
- 2991US9691707B2Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor packageSTATS CHIPPAC LTD·Filed 2016·Granted Jun 27, 2017·5 cites·24 claims
- 3091US9406531B1Integrated circuit packaging system with photoimagable dielectric-defined trace and method of manufacture thereofCAMACHO ZIGMUND RAMIREZ·Filed 2014·Granted Aug 2, 2016·11 cites·9 claims
- 3191US8421203B2Integrated circuit packaging system with foldable substrate and method of manufacture thereofCHI HEEJO·Filed 2010·Granted Apr 16, 2013·13 cites·11 claims
- 3289US9748157B1Integrated circuit packaging system with joint assembly and method of manufacture thereofSTATS CHIPPAC PTE LTD·Filed 2013·Granted Aug 29, 2017·10 cites·20 claims
- 3389US9064859B2Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframeSTATS CHIPPAC LTD·Filed 2012·Granted Jun 23, 2015·8 cites·26 claims
- 3489US8455300B2Integrated circuit package system with embedded die superstructure and method of manufacture thereofCHI HEEJO·Filed 2010·Granted Jun 4, 2013·12 cites·14 claims
- 3588US9859200B2Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereofSTATS CHIPPAC PTE LTD·Filed 2015·Granted Jan 2, 2018·8 cites·10 claims
- 3688US9391046B2Semiconductor device and method of forming 3D semiconductor package with semiconductor die stacked over semiconductor waferPARK YEONGLM·Filed 2011·Granted Jul 12, 2016·23 cites·25 claims
- 3788US8018034B2Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structureSTATS CHIPPAC LTD·Filed 2009·Granted Sep 13, 2011·13 cites·21 claims
- 3887US9287204B2Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer formSTATS CHIPPAC LTD·Filed 2013·Granted Mar 15, 2016·8 cites·25 claims
- 3987US9263332B2Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMPSTATS CHIPPAC LTD·Filed 2013·Granted Feb 16, 2016·6 cites·28 claims
- 4087US8318541B2Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor dieSHIN HANGIL·Filed 2010·Granted Nov 27, 2012·8 cites·19 claims
- 4186US9966335B2Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor dieSTATS CHIPPAC LTD·Filed 2015·Granted May 8, 2018·4 cites·9 claims
- 4286US9252130B2Methods of manufacturing flip chip semiconductor packages using double-sided thermal compression bondingSTATS CHIPPAC LTD·Filed 2013·Granted Feb 2, 2016·10 cites·27 claims
- 4386US8476111B2Integrated circuit packaging system with intra substrate die and method of manufacture thereofCHO NAMJU·Filed 2011·Granted Jul 2, 2013·8 cites·10 claims
- 4486US8421210B2Integrated circuit packaging system with dual side connection and method of manufacture thereofCHI HEEJO·Filed 2010·Granted Apr 16, 2013·9 cites·20 claims
- 4584US9558965B2Semiconductor device with thin profile WLCSP with vertical interconnect over package footprintCHI HEEJO·Filed 2012·Granted Jan 31, 2017·5 cites·19 claims
- 4684US9406533B2Methods of forming conductive and insulating layersSTATS CHIPPAC LTD·Filed 2013·Granted Aug 2, 2016·6 cites·25 claims
- 4784US9245770B2Semiconductor device and method of simultaneous molding and thermalcompression bondingSTATS CHIPPAC LTD·Filed 2013·Granted Jan 26, 2016·7 cites·24 claims
- 4883US9299650B1Integrated circuit packaging system with single metal layer interposer and method of manufacture thereofCHI HEEJO·Filed 2013·Granted Mar 29, 2016·6 cites·20 claims
- 4982US9153476B2Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor dieSTATS CHIPPAC LTD·Filed 2012·Granted Oct 6, 2015·5 cites·25 claims
- 5081US8749040B2Integrated circuit packaging system with package-on-package and method of manufacture thereofCHI HEEJO·Filed 2009·Granted Jun 10, 2014·9 cites·9 claims
Showing the top 50 of 99 patent records by PatentIndex Score.
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