Inventor · disambiguated record
Vidya Rajagopalan
Also filed as: RAJAGOPALAN VIDYA
12 granted patents·2 pending applications·305 citations·filing 1992–2025
92Inventor score
Files withMIPS TECH INC8DIGITAL EQUIPMENT CORP2RIVIAN IP HOLDINGS LLC2KISHORE KARAGADA RAMARAO1YU MENG-BING1
Top patents by PatentIndex Score
14 records- 0192US7594079B2Data cache virtual hint way prediction, and applications thereofMIPS TECH INC·Filed 2006·Granted Sep 22, 2009·26 cites·22 claims
- 0289US12374127B2Heterogeneous on-vehicle camera system for object detectionRIVIAN IP HOLDINGS LLC·Filed 2022·Granted Jul 29, 2025·1 cites·17 claims
- 0389US9092343B2Data cache virtual hint way prediction, and applications thereofYU MENG-BING·Filed 2009·Granted Jul 28, 2015·19 cites·12 claims
- 0481US6493776B1Scalable on-chip system busMIPS TECH INC·Filed 1999·Granted Dec 10, 2002·95 cites·28 claims
- 0580US7711934B2Processor core and method for managing branch misprediction in an out-of-order processor pipelineMIPS TECH INC·Filed 2005·Granted May 4, 2010·11 cites·16 claims
- 0677US2025308262A1Heterogeneous on-vehicle camera system for object detectionRIVIAN IP HOLDINGS LLC·Filed 2025·Application pending·0 cites
- 0776US7124072B1Program counter and data tracing from a multi-issue processorMIPS TECH INC·Filed 2001·Granted Oct 17, 2006·22 cites·21 claims
- 0872US7159101B1System and method to trace high performance multi-issue processorsMIPS TECH INC·Filed 2003·Granted Jan 2, 2007·17 cites·11 claims
- 0969US8078846B2Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidatedKISHORE KARAGADA RAMARAO·Filed 2006·Granted Dec 13, 2011·6 cites·14 claims
- 1069US6732208B1Low latency system bus interface for multi-master processing environmentsMIPS TECH INC·Filed 1999·Granted May 4, 2004·62 cites·31 claims
- 1165US7721075B2Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addressesMIPS TECH INC·Filed 2006·Granted May 18, 2010·3 cites·35 claims
- 1262US5155382ATwo-stage CMOS latch with single-wire clockDIGITAL EQUIPMENT CORP·Filed 1992·Granted Oct 13, 1992·18 cites·14 claims
- 1352US5341319AMethod and apparatus for controlling a rounding operation in a floating point multiplier circuitDIGITAL EQUIPMENT CORP·Filed 1993·Granted Aug 23, 1994·25 cites·14 claims
- 1450US2007089095A1Apparatus and method to trace high performance multi-issue processorsMIPS TECH INC·Filed 2006·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →