Apparatus and method to trace high performance multi-issue processors

Abstract

A system and method for program counter and data tracing in a multi-issue processor is disclosed. Instructions are traced in program sequence order. In one embodiment instructions are traced in graduation order from a reorder buffer. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

1 . A computer program product having a computer-usable medium storing computer-readable program code, the computer-readable program code comprising: 
 computer-readable program code for causing a computer to describe a reorder buffer in a multi-issue processor core having a plurality of instruction pipelines, said reorder buffer having a graduation cycle for graduating instructions in program order in which the maximum number of instructions graduating per cycle depends on the number of issue slots of said multi-issue processor core; and    computer-readable program code for causing a computer to describe a trace generation module that transmits trace data for said instructions in graduation order for each graduation cycle along with information that enables a determination of program execution of said instructions.    
     
     
         2 . The computer program product of  claim 1 , further comprising: computer-readable program code for causing said trace generation module to assign each instruction in the graduation cycle to one of a plurality of trace buses such that the relative instruction order of graduating instructions may be determined from associated trace bus numbers of said plurality of trace buses.  
     
     
         3 . The computer program product of  claim 2 , further comprising: computer-readable program code for causing said trace generation module to coordinate transaction end points on said plurality of trace buses such that a sequence of program data may be determined.  
     
     
         4 . A method for enabling a computer to generate tracing logic, comprising: 
 transmitting computer-readable program code to a computer-readable medium associated with a computer, said computer-readable program code including: 
 computer-readable program code for causing a computer reading said computer-readable memory to describe a reorder buffer in a multi-issue processor core having a plurality of instruction pipelines, said reorder buffer having a graduation cycle for graduating instructions in program order in which the maximum number of instructions graduating per cycle depends on the number of issue slots of said multi-issue processor core; and  
 computer-readable program code for causing a computer reading said computer-readable memory to describe a trace generation module that transmits trace data for said instructions in graduation order for each graduation cycle along with information that enables a determination of program execution of said instructions.  
   
     
     
         5 . The method of  claim 4 , wherein computer-readable program code is transmitted to said computer over the Internet.  
     
     
         6 . A computer data signal embodied in a transmission medium comprising: 
 computer-readable program code for causing a computer storing said data signal in a computer-readable medium to describe a reorder buffer in a multi-issue processor core having a plurality of instruction pipelines, said reorder buffer having a graduation cycle for graduating instructions in program order said reorder buffer having a graduation cycle in which the maximum number of instructions graduating per cycle depends on the number of issue slots of said multi-issue processor core; and    computer-readable program code for causing a computer storing said data signal in a computer-readable medium to describe a trace generation module that transmits trace data for said instructions in graduation order for each graduation cycle along with information that enables a determination of program execution of said instructions.    
     
     
         7 . The computer data signal of  claim 6 , further comprising: computer-readable program code for causing said trace generation module to assign each instruction in the graduation cycle to one of a plurality of trace buses such that the relative instruction order of graduating instructions may be determined from associated trace bus numbers of said plurality of trace buses.  
     
     
         8 . The computer data signal of  claim 7 , further comprising: computer-readable program code for causing said trace generation module to coordinate transaction end points on said plurality of trace buses such that a sequence of program data may be determined.  
     
     
         9 . A tracing system, comprising: 
 an embedded processor, said embedded processor including, a multi-issue processor core having a plurality of instruction pipelines for executing instructions and having a reorder buffer placing out-of-order issued instructions placed in program sequence order, said reorder buffer having a graduation cycle in which the maximum number of instructions graduating per cycle depends on the number of issue slots of said multi-issue processor core; and    trace generation logic that is operative to generate trace data for said instructions executing in said multi-issue processor core, said trace generation logic monitoring the reorder buffer and tracing executed instructions according to a graduation cycle associated with the reorder buffer.