Inventor · disambiguated record
Jonathan H. Griffith
Also filed as: GRIFFITH JONATHAN H
17 granted patents·5 pending applications·437 citations·filing 1985–2017
94Inventor score
Top patents by PatentIndex Score
22 records- 0197US6531069B1Reactive Ion Etching chamber design for flip chip interconnectionsIBM·Filed 2000·Granted Mar 11, 2003·144 cites·16 claims
- 0290US6293457B1Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallizationIBM·Filed 2000·Granted Sep 25, 2001·86 cites·23 claims
- 0385US5277749AMethods and apparatus for relieving stress and resisting stencil delamination when performing lift-off processes that utilize high stress metals and/or multiple evaporation stepsIBM·Filed 1991·Granted Jan 11, 1994·132 cites·19 claims
- 0482US7144490B2Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layerIBM·Filed 2003·Granted Dec 5, 2006·14 cites·7 claims
- 0578US9613842B2Wafer handler and methods of manufactureIBM·Filed 2014·Granted Apr 4, 2017·3 cites·14 claims
- 0675US8753460B2Reduction of edge chipping during wafer handlingKNICKERBOCKER SARAH H·Filed 2011·Granted Jun 17, 2014·4 cites·5 claims
- 0772US7473997B2Method for forming robust solder interconnect structures by reducing effects of seed layer underetchingIBM·Filed 2005·Granted Jan 6, 2009·4 cites·10 claims
- 0872US6228665B1Method of measuring oxide thickness during semiconductor fabricationIBM·Filed 2000·Granted May 8, 2001·14 cites·18 claims
- 0967US8807184B2Reduction of edge chipping during wafer handlingIBM·Filed 2013·Granted Aug 19, 2014·1 cites·5 claims
- 1065US8314500B2Interconnections for flip-chip using lead-free solders and having improved reaction barrier layersBELANGER LUC·Filed 2006·Granted Nov 20, 2012·4 cites·1 claims
- 1162US6995475B2I/C chip suitable for wire bondingIBM·Filed 2003·Granted Feb 7, 2006·9 cites·3 claims
- 1259US7932169B2Interconnection for flip-chip using lead-free solders and having improved reaction barrier layersIBM·Filed 2009·Granted Apr 26, 2011·1 cites·3 claims
- 1354US10049909B2Wafer handler and methods of manufactureGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 14, 2018·0 cites·17 claims
- 1450US6992389B2Barrier for interconnect and methodIBM·Filed 2004·Granted Jan 31, 2006·4 cites·10 claims
- 1548US4588471AProcess for etching composite chrome layersIBM·Filed 1985·Granted May 13, 1986·17 cites·24 claims
- 1646US7572726B2Method of forming a bond pad on an I/C chip and resulting structureIBM·Filed 2005·Granted Aug 11, 2009·0 cites·15 claims
- 1746US2006249854A1Device with area array pads for test probingCHENG TIEN-JEN·Filed 2006·Application pending·0 cites
- 1845US7767575B2Forming robust solder interconnect structures by reducing effects of seed layer underetchingTESSERA INTELLECTUAL PROPERTIE·Filed 2009·Granted Aug 3, 2010·0 cites·5 claims
- 1940US2005167837A1Device with area array pads for test probingIBM·Filed 2004·Application pending·0 cites
- 2039US2005026416A1Encapsulated pin structure for improved reliability of waferIBM·Filed 2003·Application pending·0 cites
- 2137US2005104208A1Stabilizing copper overlayer for enhanced c4 interconnect reliabilityIBM·Filed 2003·Application pending·0 cites
- 2234US2002190028A1Method of improving uniformity of etching of a film on an articleIBM·Filed 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →