Inventor · disambiguated record
Vito Dai
Also filed as: DAI VITO
16 granted patents·1 pending application·80 citations·filing 2006–2020
91Inventor score
Files withGLOBALFOUNDRIES INC6MOTIVO INC4ADVANCED MICRO DEVICES INC1GLOBALFOUNDRIES SG PTE LTD1TEOH KAH CHING EDWARD1
Top patents by PatentIndex Score
17 records- 0188US8898606B1Layout pattern correction for integrated circuitsGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 25, 2014·18 cites·20 claims
- 0287US8555215B2Methods for decomposing circuit design layouts and for fabricating semiconductor devices using decomposed patternsZOU YI·Filed 2012·Granted Oct 8, 2013·8 cites·18 claims
- 0386US8418105B1Methods for pattern matching in a double patterning technology-compliant physical design flowWANG LYNN T·Filed 2012·Granted Apr 9, 2013·13 cites·15 claims
- 0482US8924896B2Automated design layout pattern correction based on context-aware patternsWANG LYNN·Filed 2013·Granted Dec 30, 2014·8 cites·16 claims
- 0577US10339254B2Integrated circuit design systems and methodsMOTIVO INC·Filed 2018·Granted Jul 2, 2019·2 cites·20 claims
- 0676US9081919B2Design-for-manufacturing—design-enabled-manufacturing (DFM-DEM) proactive integrated manufacturing flowGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Jul 14, 2015·7 cites·21 claims
- 0775US9012270B2Metal layer enabling directed self-assembly semiconductor layout designsXU JI·Filed 2013·Granted Apr 21, 2015·6 cites·11 claims
- 0875US7757190B2Design rules checking augmented with pattern matchingADVANCED MICRO DEVICES INC·Filed 2006·Granted Jul 13, 2010·8 cites·12 claims
- 0974US8453089B2Method and apparatus for pattern adjusted timing via pattern matchingTEOH KAH CHING EDWARD·Filed 2011·Granted May 28, 2013·6 cites·20 claims
- 1067US9009634B2Methods for fabricating integrated circuits including generating photomasks for directed self-assemblyGLOBALFOUNDRIES INC·Filed 2013·Granted Apr 14, 2015·1 cites·20 claims
- 1166US9170501B2Methods for fabricating integrated circuits including generating photomasks for directed self-assemblyGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 27, 2015·1 cites·19 claims
- 1265US9023730B1Methods for fabricating integrated circuits including generating e-beam patterns for directed self-assemblyGLOBALFOUNDRIES INC·Filed 2013·Granted May 5, 2015·1 cites·20 claims
- 1363US8910090B2Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applicationsGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 9, 2014·1 cites·11 claims
- 1460US11714944B2Optimization of physical cell placement for integrated circuitsMOTIVO INC·Filed 2020·Granted Aug 1, 2023·0 cites·15 claims
- 1557US10936778B2And optimization of physical cell placementMOTIVO INC·Filed 2018·Granted Mar 2, 2021·0 cites·13 claims
- 1650US9959380B2Integrated circuit design systems and methodsMOTIVO INC·Filed 2016·Granted May 1, 2018·0 cites·20 claims
- 1746US2015286763A1Pattern matching for predicting defect limited yieldGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →