Inventor · disambiguated record
Gustavo E. Tellez
Also filed as: TELLEZ GUSTAVO · TELLEZ GUSTAVO E · TELLEZ GUSTAVO ENRIQUE
53 granted patents·3 pending applications·641 citations·filing 1998–2022
98Inventor score
Top patents by PatentIndex Score
56 records- 0195US9158885B1Reducing color conflicts in triple patterning lithographyIBM·Filed 2014·Granted Oct 13, 2015·52 cites·20 claims
- 0294US6738954B1Method for prediction random defect yields of integrated circuits with accuracy and computation time controlsIBM·Filed 2000·Granted May 18, 2004·98 cites·36 claims
- 0392US11120192B1White space insertion for enhanced routabilityIBM·Filed 2020·Granted Sep 14, 2021·5 cites·20 claims
- 0492US10223496B2Triple and quad coloring shape layoutsIBM·Filed 2017·Granted Mar 5, 2019·7 cites·9 claims
- 0588US6247853B1Incremental method for critical area and critical region computation of via blocksIBM·Filed 1998·Granted Jun 19, 2001·100 cites·14 claims
- 0685US6189132B1Design rule correction system and methodIBM·Filed 1998·Granted Feb 13, 2001·126 cites·32 claims
- 0784US11983476B2Technology-independent line end routingIBM·Filed 2021·Granted May 14, 2024·1 cites·20 claims
- 0883US12423502B2Rule check heatmap predictionIBM·Filed 2022·Granted Sep 23, 2025·1 cites·20 claims
- 0983US10747935B2Identification of hotspots in congestion analysis during physical design of integrated circuitIBM·Filed 2019·Granted Aug 18, 2020·3 cites·20 claims
- 1081US6986109B2Practical method for hierarchical-preserving layout optimization of integrated circuit layoutIBM·Filed 2003·Granted Jan 10, 2006·38 cites·35 claims
- 1180US6941528B2Use of a layout-optimization tool to increase the yield and reliability of VLSI designsIBM·Filed 2003·Granted Sep 6, 2005·29 cites·27 claims
- 1279US9245076B2Orthogonal circuit element routingIBM·Filed 2013·Granted Jan 26, 2016·5 cites·20 claims
- 1378US6993692B2Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memoriesIBM·Filed 2003·Granted Jan 31, 2006·25 cites·21 claims
- 1477US8347257B2Detailed routability by cell placementIBM·Filed 2010·Granted Jan 1, 2013·5 cites·24 claims
- 1576US10831972B2Capacity model for global routingIBM·Filed 2019·Granted Nov 10, 2020·1 cites·17 claims
- 1675US8938702B1Timing driven routing for noise reduction in integrated circuit designIBM·Filed 2013·Granted Jan 20, 2015·5 cites·20 claims
- 1774US11341311B1Generation and selection of universally routable via mesh specifications in an integrated circuitIBM·Filed 2021·Granted May 24, 2022·1 cites·20 claims
- 1874US8230378B2Method for IC wiring yield optimization, including wire widening during and after routingCOHN JOHN M·Filed 2009·Granted Jul 24, 2012·5 cites·15 claims
- 1974US7076749B2Method and system for improving integrated circuit manufacturing productivityIBM·Filed 2004·Granted Jul 11, 2006·22 cites·20 claims
- 2072US10796064B2Autonomous placement to satisfy self-aligned double patterning constraintsIBM·Filed 2018·Granted Oct 6, 2020·1 cites·20 claims
- 2172US10726187B2Self-aligned double patterning-aware routing in chip manufacturingIBM·Filed 2018·Granted Jul 28, 2020·2 cites·17 claims
- 2272US10229239B2Capacity model for global routingIBM·Filed 2017·Granted Mar 12, 2019·1 cites·17 claims
- 2372US7895545B2Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learningIBM·Filed 2008·Granted Feb 22, 2011·5 cites·8 claims
- 2471US7062729B2Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimizationIBM·Filed 2004·Granted Jun 13, 2006·16 cites·17 claims
- 2566US10503841B2Integrated circuit buffering solutions considering sink delaysIBM·Filed 2019·Granted Dec 10, 2019·0 cites·20 claims
- 2666US10496764B2Integrated circuit buffering solutions considering sink delaysIBM·Filed 2019·Granted Dec 3, 2019·0 cites·20 claims
- 2763US12277375B2Power staple avoidance for routing via reductionIBM·Filed 2022·Granted Apr 15, 2025·0 cites·20 claims
- 2862US12417333B2Short net pin alignment for routingIBM·Filed 2022·Granted Sep 16, 2025·0 cites·20 claims
- 2962US10372836B2Integrated circuit buffering solutions considering sink delaysIBM·Filed 2017·Granted Aug 6, 2019·0 cites·19 claims
- 3062US10372837B2Integrated circuit buffering solutions considering sink delaysIBM·Filed 2018·Granted Aug 6, 2019·0 cites·1 claims
- 3162US6904575B2Method for improving chip yields in the presence of via flaringIBM·Filed 2002·Granted Jun 7, 2005·8 cites·27 claims
- 3262US6305004B1Method for improving wiring related yield and capacitance properties of integrated circuits by maze-routingIBM·Filed 1999·Granted Oct 16, 2001·47 cites·10 claims
- 3361US10719656B2Triple and quad coloring of shape layoutsIBM·Filed 2019·Granted Jul 21, 2020·0 cites·18 claims
- 3461US10606978B2Triple and quad coloring of shape layoutsIBM·Filed 2017·Granted Mar 31, 2020·0 cites·8 claims
- 3561US10346558B2Integrated circuit buffering solutions considering sink delaysIBM·Filed 2017·Granted Jul 9, 2019·0 cites·20 claims
- 3661US7117456B2Circuit area minimization using scalingIBM·Filed 2003·Granted Oct 3, 2006·7 cites·20 claims
- 3760US11734486B2Sweepline triangulation for spanning graphsIBM·Filed 2021·Granted Aug 22, 2023·0 cites·20 claims
- 3860US8448110B2Method to reduce delay variation by sensitivity cancellationHABITZ PETER A·Filed 2009·Granted May 21, 2013·2 cites·24 claims
- 3960US7657859B2Method for IC wiring yield optimization, including wire widening during and after routingIBM·Filed 2005·Granted Feb 2, 2010·1 cites·19 claims
- 4059US7961932B2Method and apparatus for manufacturing diamond shaped chipsIBM·Filed 2007·Granted Jun 14, 2011·1 cites·4 claims
- 4159US7725864B2Systematic yield in semiconductor manufactureIBM·Filed 2007·Granted May 25, 2010·1 cites·16 claims
- 4259US7721240B2Systematic yield in semiconductor manufactureIBM·Filed 2007·Granted May 18, 2010·1 cites·15 claims
- 4359US7337415B2Systematic yield in semiconductor manufactureIBM·Filed 2004·Granted Feb 26, 2008·5 cites·21 claims
- 4459US2019138683A1Capacity model for global routingIBM·Filed 2019·Application pending·0 cites
- 4558US12493730B2Timing-aware and simultaneous optimization of latch clustering and placement in an integrated circuitIBM·Filed 2022·Granted Dec 9, 2025·0 cites·15 claims
- 4658US11829697B2Region-based layout routingIBM·Filed 2021·Granted Nov 28, 2023·0 cites·18 claims
- 4757US11087062B1Dynamic SADP region generationIBM·Filed 2020·Granted Aug 10, 2021·0 cites·20 claims
- 4853US11966682B2Fast independent checker for extreme ultraviolet (EUV) routingIBM·Filed 2021·Granted Apr 23, 2024·0 cites·20 claims
- 4950US8631375B2Via selection in integrated circuit designARELT ROBERT R·Filed 2012·Granted Jan 14, 2014·1 cites·20 claims
- 5047US11074379B2Multi-cycle latch tree synthesisIBM·Filed 2019·Granted Jul 27, 2021·0 cites·20 claims
Showing the top 50 of 56 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →