Capacity model for global routing

Abstract

A global router determines edge capacity of global tiles for a first integrated circuit in a global routing operation. The global router determines a respective edge capacity of minimum width wire tracks for each of a plurality of global tiles in a first metal layer in the first integrated circuit. Next, the global router determines a respective edge capacity of non-minimum width wire tracks for each of the plurality of global tiles in the first metal layer in the first integrated circuit. The edge capacities for minimum width and non-minimum width wire tracks are determined in separate operations within the global routing operation for fabrication of an integrated circuit.

Having described our invention, what we now claim is as follows: 
     
         1 . A method for determining edge capacity of global tiles in a global routing operation for a first integrated circuit, comprising:
 determining a respective edge capacity of minimum width wire tracks for each of a plurality of global tiles in a first metal layer in the first integrated circuit in the global routing operation;   determining a respective edge capacity of non-minimum width wire tracks for each of the plurality of global tiles in the first metal layer in the first integrated circuit in the global routing operation; and   wherein edge capacities for minimum width and non-minimum width wire tracks are determined in separate operations within the global routing operation for fabrication of an integrated circuit.   
     
     
         2 . The method as recited in  claim 1 , further comprising:
 determining a respective via capacity of minimum width vias for each of a plurality of global tiles in a first metal layer in the first integrated circuit, wherein the minimum width vias capacity represents minimum width vias which electrically connect the first metal layer to a second metal layer;   determining a respective edge capacity of non-minimum width vias for each of the plurality of global tiles in the first metal layer in the first integrated circuit, wherein the non-minimum width vias capacity represents non-minimum width vias which electrically connect the first metal layer to a second metal layer; and   wherein via capacities for minimum width and non-minimum width vias are determined in separate operations.   
     
     
         3 . The method as recited in  claim 2 , wherein respective via capacities for vias between respective metal layers are computed as the product of a number of wire tracks of a respective width in a global tile in the first metal layer and a number of wire tracks of the respective width in a global tile in the second metal layer. 
     
     
         4 . The method as recited in  claim 1 , wherein a respective edge capacity of minimum width wire tracks between a first global and a second global tile in the first metal layer and a respective edge capacity of non-minimum width wire tracks between the first global and the second global tile in the first metal layer are represented in a vector, wherein respective elements of the vector represent a respective edge capacity of the minimum wire track thickness and the non-minimum wire track thickness. 
     
     
         5 . The method as recited in  claim 4 , wherein the non-minimum width wire tracks comprise a plurality of different non-minimum width wire track widths, and the method further comprises:
 determining a respective edge capacity of each of the non-minimum width wire track widths for each of the plurality of global tiles in the first metal layer in the first integrated circuit; and   wherein edge capacities for each of the non-minimum width wire track widths are determined in separate operations.   
     
     
         6 . The method as recited in  claim 1 , wherein the edge capacities are determined for the first metal layer before repeating the determining for a second metal layer. 
     
     
         7 . The method as recited in  claim 1 , further comprising embedding a plurality of nets in a global routing graph based on the determined edge and via capacities. 
     
     
         8 . The method as recited in  claim 1 , further comprising, by a detailed routing module, placing a set of detail wires for each net of the plurality of nets inside the minimum width and non-minimum width wire tracks in the global routing tiles in the first metal layer. 
     
     
         9 . A computer readable memory storing a control program for controlling a global routing operation for determining edge capacity of global tiles in a first integrated circuit, said control program causing a processor to perform the method comprising:
 determining a respective edge capacity of minimum width wire tracks for each of a plurality of global tiles in a first metal layer in the first integrated circuit in the global routing operation;   determining a respective edge capacity of non-minimum width wire tracks for each of the plurality of global tiles in the first metal layer in the first integrated circuit in the global routing operation; and   wherein edge capacities for minimum width and non-minimum width wire tracks are determined in separate operations with the global routing operation for fabrication of an integrated circuit.   
     
     
         10 . The computer readable memory as recited in  claim 9 , further comprising:
 determining a respective via capacity of minimum width vias for each of a plurality of global tiles in a first metal layer in the first integrated circuit, wherein the minimum width vias capacity represents minimum width vias which electrically connect the first metal layer to a second metal layer;   determining a respective edge capacity of non-minimum width vias for each of the plurality of global tiles in the first metal layer in the first integrated circuit, wherein the non-minimum width vias capacity represents non-minimum width vias which electrically connect the first metal layer to a second metal layer; and   wherein via capacities for minimum width and non-minimum width vias are determined in separate operations.   
     
     
         11 . The computer readable memory as recited in  claim 10 , wherein respective via capacities for vias between respective metal layers are computed as the product of a number of wire tracks of a respective width in a global tile in the first metal layer and a number of wire tracks of the respective width in a global tile in the second metal layer. 
     
     
         12 . The computer readable memory as recited in  claim 9 , wherein a respective edge capacity of minimum width wire tracks between a first global and a second global tile in the first metal layer and a respective edge capacity of non-minimum width wire tracks between the first global and the second global tile in the first metal layer are represented in a vector, wherein respective elements of the vector represent a respective edge capacity of the minimum wire track thickness and the non-minimum wire track thickness. 
     
     
         13 . The computer readable memory as recited in  claim 12 , wherein the non-minimum width wire tracks comprise a plurality of different non-minimum width wire track widths, and the method further comprises:
 determining a respective edge capacity of each of the non-minimum width wire track widths for each of the plurality of global tiles in the first metal layer in the first integrated circuit; and   wherein edge capacities for each of the non-minimum width wire track widths are determined in separate operations.   
     
     
         14 . The computer readable memory as recited in  claim 9 , further comprising, a detailed routing module for placing a set of detail wires for each net of the plurality of nets in the first metal layer inside the minimum width and non-minimum width wire tracks in the global routing tiles. 
     
     
         15 . Apparatus, comprising:
 a processor;   a computer memory holding computer program instructions executed by the processor for controlling a global routing operation for determining edge capacity of global tiles in a first integrated circuit, the computer program instructions when executed carrying out the actions comprising:   determining a respective edge capacity of minimum width wire tracks for each of a plurality of global tiles in a first metal layer in the first integrated circuit in the global routing operation;   determining a respective edge capacity of non-minimum width wire tracks for each of the plurality of global tiles in the first metal layer in the first integrated circuit in the global routing operation; and   wherein edge capacities for minimum width and non-minimum width wire tracks are determined in separate operations within the global routing operation for fabrication of an integrated circuit.   
     
     
         16 . The apparatus as recited in  claim 15 , wherein the actions further comprise:
 determining a respective via capacity of minimum width vias for each of a plurality of global tiles in a first metal layer in the first integrated circuit, wherein the minimum width vias capacity represents minimum width vias which electrically connect the first metal layer to a second metal layer;   determining a respective edge capacity of non-minimum width vias for each of the plurality of global tiles in the first metal layer in the first integrated circuit, wherein the non-minimum width vias capacity represents non-minimum width vias which electrically connect the first metal layer to a second metal layer; and   wherein via capacities for minimum width and non-minimum width vias are determined in separate operations.   
     
     
         17 . The apparatus as recited in  claim 16 , wherein the actions further comprise determining respective via capacities for vias between respective metal layers from the product of a number of wire tracks of a respective width in a global tile in the first metal layer and a number of wire tracks of the respective width in a global tile in the second metal layer. 
     
     
         18 . The apparatus as recited in  claim 17 , wherein the non-minimum width wire tracks comprise a plurality of different non-minimum width wire track widths, and the actions further comprise:
 determining a respective edge capacity of each of the non-minimum width wire track widths for each of the plurality of global tiles in the first metal layer in the first integrated circuit; and   wherein edge capacities for each of the non-minimum width wire track widths are determined in separate operations.   
     
     
         19 . The apparatus as recited in  claim 15 , wherein the actions further comprise embedding a plurality of nets in a global routing graph of the first metal layer based on the determined edge and via capacities. 
     
     
         20 . The apparatus as recited in  claim 16 , wherein the actions further comprise placing a set of detail wires for each net of the plurality of nets in the first metal layer inside the minimum width and non-minimum width wire tracks in the global routing tiles.