Inventor · disambiguated record
Charles J. Alpert
Also filed as: ALPERT CHARLES · ALPERT CHARLES J · ALPERT CHARLES JAY
121 granted patents·12 pending applications·1,563 citations·filing 1997–2023
99Inventor score
Files withIBM70CADENCE DESIGN SYSTEMS INC29ALPERT CHARLES J18ALPERT CHARLES JAY12AGARWAL KANAK BEHARI1
Top patents by PatentIndex Score
133 records- 0195US7549137B2Latch placement for high performance and low power circuitsIBM·Filed 2006·Granted Jun 16, 2009·43 cites·12 claims
- 0294US6347393B1Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computationIBM·Filed 1999·Granted Feb 12, 2002·230 cites·22 claims
- 0394US6117182AOptimum buffer placement for noise avoidanceIBM·Filed 1998·Granted Sep 12, 2000·229 cites·22 claims
- 0493US8677299B1Latch clustering with proximity to local clock buffersIBM·Filed 2013·Granted Mar 18, 2014·22 cites·17 claims
- 0593US7065730B2Porosity aware buffered steiner tree constructionIBM·Filed 2003·Granted Jun 20, 2006·95 cites·8 claims
- 0692US8954912B2Structured placement of latches/flip-flops to minimize clock power in high-performance designsIBM·Filed 2012·Granted Feb 10, 2015·18 cites·25 claims
- 0792US8495548B2Multi-patterning lithography aware cell placement in integrated circuit designAGARWAL KANAK BEHARI·Filed 2011·Granted Jul 23, 2013·22 cites·20 claims
- 0891US8793636B2Placement of structured netsALPERT CHARLES J·Filed 2011·Granted Jul 29, 2014·17 cites·23 claims
- 0990US7624366B2Clock aware placementIBM·Filed 2006·Granted Nov 24, 2009·27 cites·34 claims
- 1089US10282506B1Systems and methods for clock tree clusteringCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 7, 2019·6 cites·20 claims
- 1189US6996512B2Practical methodology for early buffer and wire resource allocationIBM·Filed 2001·Granted Feb 7, 2006·60 cites·21 claims
- 1288US10643019B1View pruning for routing tree optimizationCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted May 5, 2020·6 cites·20 claims
- 1388US10216880B1Systems and methods for power efficient flop clusteringCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Feb 26, 2019·6 cites·20 claims
- 1488US8782584B2Post-placement cell shiftingIBM·Filed 2013·Granted Jul 15, 2014·10 cites·1 claims
- 1588US7299442B2Probabilistic congestion prediction with partial blockagesIBM·Filed 2005·Granted Nov 20, 2007·19 cites·18 claims
- 1687US8365120B2Resolving global coupling timing and slew violations for buffer-dominated designsIBM·Filed 2010·Granted Jan 29, 2013·11 cites·21 claims
- 1787US6401234B1Method and system for re-routing interconnects within an integrated circuit design having blockages and baysIBM·Filed 1999·Granted Jun 4, 2002·132 cites·21 claims
- 1886US12423501B1Skewing level limited clock treeCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Sep 23, 2025·1 cites·20 claims
- 1986US10102328B1System and method for constructing spanning treesCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 16, 2018·5 cites·17 claims
- 2086US8881089B1Physical synthesis optimization with fast metric checkIBM·Filed 2013·Granted Nov 4, 2014·11 cites·14 claims
- 2186US8667441B2Clock optimization with local clock buffer control optimizationALPERT CHARLES J·Filed 2010·Granted Mar 4, 2014·10 cites·20 claims
- 2286US7934188B2Legalization of VLSI circuit placement with blockages using hierarchical row slicingIBM·Filed 2008·Granted Apr 26, 2011·16 cites·18 claims
- 2385US10402522B1Region aware clusteringCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Sep 3, 2019·4 cites·20 claims
- 2485US10289797B1Local cluster refinementCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 14, 2019·4 cites·20 claims
- 2585US8418113B1Consideration of local routing and pin access during VLSI global routingALPERT CHARLES J·Filed 2011·Granted Apr 9, 2013·9 cites·24 claims
- 2685US8010926B2Clock power minimization with regular physical placement of clock repeater componentsIBM·Filed 2008·Granted Aug 30, 2011·15 cites·17 claims
- 2784US12393760B1Wire density-aware layer assignmentCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Aug 19, 2025·1 cites·20 claims
- 2884US12061857B1Post-CTS insertion delay and skew target reformulation of clock treeCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Aug 13, 2024·1 cites·20 claims
- 2984US10354183B2Power-driven synthesis under latency constraintsIBM·Filed 2014·Granted Jul 16, 2019·5 cites·18 claims
- 3084US10031994B1Systems and methods for congestion and routability aware detailed placementCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jul 24, 2018·5 cites·18 claims
- 3183US10289795B1Routing tree topology generationCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 14, 2019·4 cites·20 claims
- 3283US10095824B1Systems and methods for symmetric H-tree construction with complicated routing blockagesCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 9, 2018·4 cites·20 claims
- 3383US9092591B2Automatic generation of wire tag lists for a metal stackIBM·Filed 2014·Granted Jul 28, 2015·6 cites·19 claims
- 3483US8589848B2Datapath placement using tiered assignmentALPERT CHARLES J·Filed 2012·Granted Nov 19, 2013·7 cites·25 claims
- 3583US7707530B2Incremental timing-driven, physical-synthesis using discrete optimizationIBM·Filed 2007·Granted Apr 27, 2010·13 cites·15 claims
- 3682US8949762B1Computer-based modeling of integrated circuit congestion and wire distribution for products and servicesIBM·Filed 2013·Granted Feb 3, 2015·5 cites·10 claims
- 3782US8826215B1Routing centric design closureIBM·Filed 2013·Granted Sep 2, 2014·6 cites·18 claims
- 3882US8769468B1Automatic generation of wire tag lists for a metal stackIBM·Filed 2013·Granted Jul 1, 2014·6 cites·23 claims
- 3982US8640075B2Early design cycle optimzationALPERT CHARLES JAY·Filed 2012·Granted Jan 28, 2014·6 cites·19 claims
- 4082US8458634B2Latch clustering with proximity to local clock buffersALPERT CHARLES JAY·Filed 2010·Granted Jun 4, 2013·7 cites·17 claims
- 4182US7484199B2Buffer insertion to reduce wirelength in VLSI circuitsIBM·Filed 2006·Granted Jan 27, 2009·9 cites·14 claims
- 4282US7467369B2Constrained detailed placementIBM·Filed 2006·Granted Dec 16, 2008·13 cites·8 claims
- 4381US10380287B1Systems and methods for modifying a balanced clock structureCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Aug 13, 2019·3 cites·20 claims
- 4481US10289775B1Systems and methods for assigning clock taps based on timingCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 14, 2019·3 cites·19 claims
- 4581US9098669B1Boundary latch and logic placement to satisfy timing constraintsIBM·Filed 2014·Granted Aug 4, 2015·7 cites·24 claims
- 4680US10402533B1Placement of cells in a multi-level routing treeCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Sep 3, 2019·3 cites·20 claims
- 4780US6915361B2Optimal buffered routing path constructions for single and multiple clock domains systemsIBM·Filed 2002·Granted Jul 5, 2005·32 cites·27 claims
- 4880US6591411B2Apparatus and method for determining buffered steiner trees for complex circuitsIBM·Filed 2001·Granted Jul 8, 2003·30 cites·45 claims
- 4979US10198551B1Clock cell library selectionCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Feb 5, 2019·3 cites·20 claims
- 5079US9875326B2Addressing coupled noise-based violations with buffering in a batch environmentIBM·Filed 2015·Granted Jan 23, 2018·3 cites·14 claims
Showing the top 50 of 133 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →