Assignee
ALPERT CHARLES J
US·14 granted patents·4 pending applications·68 citations·filing 2007–2012
Technology mixG06F18
Top patents by PatentIndex Score
18 records- 0191US8793636B2Placement of structured netsALPERT CHARLES J·Filed 2011·Granted Jul 29, 2014·17 cites·23 claims
- 0286US8667441B2Clock optimization with local clock buffer control optimizationALPERT CHARLES J·Filed 2010·Granted Mar 4, 2014·10 cites·20 claims
- 0385US8418113B1Consideration of local routing and pin access during VLSI global routingALPERT CHARLES J·Filed 2011·Granted Apr 9, 2013·9 cites·24 claims
- 0483US8589848B2Datapath placement using tiered assignmentALPERT CHARLES J·Filed 2012·Granted Nov 19, 2013·7 cites·25 claims
- 0579US8595675B1Local objective optimization in global placement of an integrated circuit designALPERT CHARLES J·Filed 2012·Granted Nov 26, 2013·5 cites·12 claims
- 0679US8495534B2Post-placement cell shiftingALPERT CHARLES J·Filed 2010·Granted Jul 23, 2013·5 cites·23 claims
- 0773US8584070B2Evaluating routing congestion based on average global edge congestion histogramsALPERT CHARLES J·Filed 2011·Granted Nov 12, 2013·3 cites·24 claims
- 0872US8418108B2Accuracy pin-slew mode for gate delay calculationALPERT CHARLES J·Filed 2011·Granted Apr 9, 2013·3 cites·15 claims
- 0971US8539400B2Routability using multiplexer structuresALPERT CHARLES J·Filed 2011·Granted Sep 17, 2013·3 cites·16 claims
- 1065US8112732B2System and computer program product for diffusion based cell placement migrationALPERT CHARLES J·Filed 2008·Granted Feb 7, 2012·3 cites·13 claims
- 1160US8091059B2Method for diffusion based cell placement migrationALPERT CHARLES J·Filed 2008·Granted Jan 3, 2012·3 cites·1 claims
- 1254US2009064080A1Buffer insertion to reduce wirelength in vlsi circuitsALPERT CHARLES J·Filed 2008·Application pending·0 cites
- 1353US2009013299A1Buffer insertion to reduce wirelength in vlsi circuitsALPERT CHARLES J·Filed 2008·Application pending·0 cites
- 1449US9524363B2Element placement in circuit design based on preferred locationALPERT CHARLES J·Filed 2012·Granted Dec 20, 2016·0 cites·19 claims
- 1546US8769457B2Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit designALPERT CHARLES J·Filed 2012·Granted Jul 1, 2014·0 cites·18 claims
- 1644US2009089721A1Method for incremental, timing-driven, physical-synthesis optimizationALPERT CHARLES J·Filed 2007·Application pending·0 cites
- 1744US2008288905A1Method and Apparatus for Congestion Based Physical SynthesisALPERT CHARLES J·Filed 2007·Application pending·0 cites
- 1837US8683411B2Electronic design automation object placement with partially region-constrained objectsALPERT CHARLES J·Filed 2010·Granted Mar 25, 2014·0 cites·25 claims
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Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →