Inventor · disambiguated record
Barry Lee Dorfman
Also filed as: DORFMAN BARRY L · DORFMAN BARRY LEE
7 granted patents·1 pending application·214 citations·filing 1992–2010
87Inventor score
Top patents by PatentIndex Score
8 records- 0184US8122404B2Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuitsSINHA DEBJIT·Filed 2009·Granted Feb 21, 2012·15 cites·16 claims
- 0279US5454000AMethod and system for authenticating filesIBM·Filed 1992·Granted Sep 26, 1995·88 cites·14 claims
- 0375US7194394B2Method and apparatus for detecting and correcting inaccuracies in curve-fitted modelsIBM·Filed 2001·Granted Mar 20, 2007·23 cites·21 claims
- 0472US6131182AMethod and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macrosIBM·Filed 1997·Granted Oct 10, 2000·72 cites·31 claims
- 0571US8201120B2Timing point selection for a static timing analysis in the presence of interconnect electrical elementsSOREFF JEFFREY P·Filed 2010·Granted Jun 12, 2012·4 cites·21 claims
- 0651US7552040B2Method and system for modeling logical circuit blocks including transistor gate capacitance loading effectsIBM·Filed 2003·Granted Jun 23, 2009·2 cites·5 claims
- 0751US2008177517A1Techniques for calculating circuit block delay and transition times including transistor gate capacitance loading effectsDORFMAN BARRY LEE·Filed 2008·Application pending·0 cites
- 0848US6005416ACompiled self-resetting CMOS logic array macrosIBM·Filed 1997·Granted Dec 21, 1999·10 cites·38 claims
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