Techniques for calculating circuit block delay and transition times including transistor gate capacitance loading effects

Abstract

Techniques for modeling delay and transition times of logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.

1 . A method for modeling, in a computer system, the behavior of a logical circuit block, the method comprising:
 first calculating in said computer system a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block and a static load capacitance value, wherein said first mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value;   second calculating in said computer system a delay time of said logical circuit block as a second mathematical function of said transistor gate capacitance and said static load capacitance value, wherein said second mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value, and wherein coefficients of said first and second mathematical functions with respect to said transistor gate capacitance are determined in conformity with a variation of said transistor gate capacitance with respect to transistor gate voltage; and   displaying by said computer system, a result of at least one of said first and second calculating.   
   
   
       2 . The method of  claim 1 , wherein said first and second mathematical functions are functions of a total capacitance and a ratio of said transistor gate capacitance to a total capacitance connected to said output of said logical circuit block, and wherein said method further comprises:
 first computing said transistor gate capacitance by multiplying said total capacitance by said ratio; and   second computing said static capacitance by subtracting said transistor gate capacitance from said total capacitance.   
   
   
       3 . The method of  claim 1 , further comprising:
 first computing a first capacitance for modeling one or more N-channel devices connected to said output of said logical circuit block;   second computing a second capacitance for modeling one or more P-channel devices connected to said output of said logical circuit block, and wherein said first and second mathematical functions are further functions of said first and second capacitances, whereby loading effects of said N-channel and P-channel devices are separately accounted for in said first and second calculating.   
   
   
       4 . The method of  claim 3 , further comprising:
 first totaling a first plurality of gate capacitances of said N-channel devices to determine said first capacitance; and   second totaling a second plurality of gate capacitances of said P-channel devices to determine said first capacitance.   
   
   
       5 . The method of  claim 1 , wherein said first and second mathematical functions are further functions of a ratio of a first capacitance of one or more N-channel devices connected to said output of said logical circuit block and a second capacitance of one or more P-channel devices connected to said output of said logical circuit block. 
   
   
       6 . A workstation computer system including a memory for storing program instructions and data, and a processor for executing said program instructions, and wherein said program instructions comprise program instructions for:
 first calculating a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block and a static load capacitance value, wherein said first mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value,   second calculating delay time of said logical circuit block as a second mathematical function of said transistor gate capacitance and said static load capacitance value, wherein said second mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value, and wherein coefficients of said first and second mathematical functions with respect to said transistor gate capacitance are determined in conformity with a variation of said transistor gate capacitance with respect to transistor gate voltage, and   displaying a result of at least one of said first and second calculating.   
   
   
       7 . The workstation computer system of  claim 6 , wherein said first and second mathematical functions are functions of a total capacitance and a ratio of said transistor gate capacitance to a total capacitance connected to said output of said logical circuit block, and wherein program instructions further comprise program instructions for:
 first computing said transistor gate capacitance by multiplying said total capacitance by said ratio; and   second computing said static capacitance by subtracting said transistor gate capacitance from said total capacitance.   
   
   
       8 . The workstation computer system of  claim 6 , wherein said program instructions further comprise program instructions for:
 first computing a first capacitance for modeling one or more N-channel devices connected to said output of said logical circuit block;   second computing a second capacitance for modeling one or more P-channel devices connected to said output of said logical circuit block, and wherein said first and second mathematical functions are further functions of said first and second capacitances, whereby loading effects of said N-channel and P-channel devices are separately accounted for in said first and second calculating.   
   
   
       9 . The workstation computer system of  claim 8 , wherein said program instructions further comprise program instructions for:
 first totaling a first plurality of gate capacitances of said N-channel devices to determine said first capacitance; and   second totaling a second plurality of gate capacitances of said P-channel devices to determine said first capacitance.   
   
   
       10 . The workstation computer system of  claim 6 , wherein said first and second mathematical functions are further functions of a ratio of a first capacitance of one or more N-channel devices connected to said output of said logical circuit block and a second capacitance of one or more P-channel devices connected to said output of said logical circuit block. 
   
   
       11 . A computer program product comprising a computer-readable storage medium encoding program instructions and data for execution on a general-purpose computer system, wherein said program instructions comprise program instructions for:
 first calculating a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block and a static load capacitance value, wherein said first mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value,   second calculating delay time of said logical circuit block as a second mathematical function of said transistor gate capacitance and said static load capacitance value, wherein said second mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value, and wherein coefficients of said first and second mathematical functions with respect to said transistor gate capacitance are determined in conformity with a variation of said transistor gate capacitance with respect to transistor gate voltage, and   displaying a result of at least one of said first and second calculating.   
   
   
       12 . The computer program product of  claim 11 , wherein said first and second mathematical functions are functions of a total capacitance and a ratio of said transistor gate capacitance to a total capacitance connected to said output of said logical circuit block, and wherein program instructions further comprise program instructions for:
 first computing said transistor gate capacitance by multiplying said total capacitance by said ratio; and   second computing said static capacitance by subtracting said transistor gate capacitance from said total capacitance.   
   
   
       13 . The computer program product of  claim 11 , wherein said program instructions further comprise program instructions for:
 first computing a first capacitance for modeling one or more N-channel devices connected to said output of said logical circuit block;   second computing a second capacitance for modeling one or more P-channel devices connected to said output of said logical circuit block, and wherein said first and second mathematical functions are further functions of said first and second capacitances, whereby loading effects of said N-channel and P-channel devices are separately accounted for in said first and second calculating.   
   
   
       14 . The computer program product of  claim 13 , wherein said program instructions further comprise program instructions for:
 first totaling a first plurality of gate capacitances of said N-channel devices to determine said first capacitance; and   second totaling a second plurality of gate capacitances of said P-channel devices to determine said first capacitance.   
   
   
       15 . The computer program product of  claim 11 , wherein said first and second mathematical functions are further functions of a ratio of a first capacitance of one or more N-channel devices connected to said output of said logical circuit block and a second capacitance of one or more P-channel devices connected to said output of said logical circuit block.