Inventor · disambiguated record
Jayashankar Bharadwaj
Also filed as: BHARADWAJ JAYASHANKAR
20 granted patents·7 pending applications·203 citations·filing 1995–2017
94Inventor score
Technology areasG06F
Top patents by PatentIndex Score
27 records- 0187US9244677B2Loop vectorization methods and apparatusINTEL CORP·Filed 2012·Granted Jan 26, 2016·9 cites·15 claims
- 0283US9733913B2Methods and systems to vectorize scalar computer program loops having loop-carried dependencesINTEL CORP·Filed 2016·Granted Aug 15, 2017·3 cites·14 claims
- 0382US9898266B2Loop vectorization methods and apparatusINTEL CORP·Filed 2016·Granted Feb 20, 2018·3 cites·20 claims
- 0481US10402177B2Methods and systems to vectorize scalar computer program loops having loop-carried dependencesINTEL CORP·Filed 2017·Granted Sep 3, 2019·2 cites·29 claims
- 0579US9268541B2Methods and systems to vectorize scalar computer program loops having loop-carried dependencesINTEL CORP·Filed 2013·Granted Feb 23, 2016·4 cites·16 claims
- 0676US9921832B2Instruction to reduce elements in a vector register with strided access patternINTEL CORP·Filed 2012·Granted Mar 20, 2018·4 cites·17 claims
- 0776US9798541B2Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask registerBHARADWAJ JAYASHANKAR·Filed 2011·Granted Oct 24, 2017·4 cites·23 claims
- 0873US9703558B2Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediateLEE VICTOR W·Filed 2011·Granted Jul 11, 2017·3 cites·14 claims
- 0969US7240342B1User transparent continuous compilationINTEL CORP·Filed 2000·Granted Jul 3, 2007·18 cites·21 claims
- 1063US5894576AMethod and apparatus for instruction scheduling to reduce negative effects of compensation codeINTEL CORP·Filed 1996·Granted Apr 13, 1999·44 cites·15 claims
- 1159US6446258B1Interactive instruction scheduling and block orderingINTLE CORP·Filed 1998·Granted Sep 3, 2002·42 cites·23 claims
- 1257US10372450B2Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediateINTEL CORP·Filed 2017·Granted Aug 6, 2019·0 cites·20 claims
- 1356US7487336B2Method for register allocation during instruction schedulingINTEL CORP·Filed 2003·Granted Feb 3, 2009·4 cites·46 claims
- 1455US9891920B2Systems, apparatuses, and methods for generating a dependency vector based on two source writemask registersINTEL CORP·Filed 2016·Granted Feb 13, 2018·0 cites·20 claims
- 1555US6675380B1Path speculating instruction schedulerINTEL CORP·Filed 1999·Granted Jan 6, 2004·34 cites·18 claims
- 1653US5787287ARepresentation of control flow and data dependence for machineINTEL CORP·Filed 1995·Granted Jul 28, 1998·27 cites·32 claims
- 1753US2018004517A1Apparatus and method for propagating conditionally evaluated values in simd/vector execution using an input mask registerINTEL CORP·Filed 2017·Application pending·0 cites
- 1852US7512930B2Program object read barrierINTEL CORP·Filed 2004·Granted Mar 31, 2009·2 cites·23 claims
- 1950US9354881B2Systems, apparatuses, and methods for generating a dependency vector based on two source writemask registersBHARADWAJ JAYASHANKAR·Filed 2011·Granted May 31, 2016·0 cites·20 claims
- 2046US9189236B2Speculative non-faulting loads and gathersBHARADWAJ JAYASHANKAR·Filed 2012·Granted Nov 17, 2015·0 cites·24 claims
- 2144US2005183079A1Tail duplicating during block layoutFiled 2004·Application pending·0 cites
- 2244US2004268095A1Efficient implementation of null reference checkFiled 2003·Application pending·0 cites
- 2343US2004194077A1Methods and apparatus to collect profile informationFiled 2003·Application pending·0 cites
- 2441US9268626B2Apparatus and method for vectorization with speculation supportBHARADWAJ JAYASHANKAR·Filed 2011·Granted Feb 23, 2016·0 cites·17 claims
- 2541US2013311530A1Apparatus and method for selecting elements of a vector computationLEE VICTOR W·Filed 2012·Application pending·0 cites
- 2640US2014089634A1Apparatus and method for detecting identical elements within a vector registerLEE VICTOR W·Filed 2011·Application pending·0 cites
- 2740US2013332701A1Apparatus and method for selecting elements of a vector computationBHARADWAJ JAYASHANKAR·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →