Apparatus and method for propagating conditionally evaluated values in simd/vector execution using an input mask register
Abstract
An apparatus and method for propagating conditionally evaluated values are disclosed. For example, a method according to one embodiment comprises: reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith; for each true value read from the input mask register, generating a first result containing the bit position of the true value; for each false value read from the input mask register following the first true value, adding the vector length of the input mask register to a bit position of the last true value read from the input mask register to generate a second result; and storing each of the first results and second results in bit positions of an output register corresponding to the bit positions read from the input mask register.
Claims
exact text as granted — not AI-modifiedWe claim:
1 . A method for propagating conditionally evaluated values comprising the operations of:
reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith; storing in an output vector register a first value related to the size of the vector register for all values in the input mask register corresponding to a true value until the first false value is encountered; storing in the output vector register for the first false value and each subsequent false value, a second value equal to the bit positions of the false values; and once the first false value is encountered, storing in the vector output register for each true value the second value associated with the last encountered false value.Join the waitlist — get patent alerts
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