Inventor · disambiguated record
Tony L. Werner
Also filed as: WERNER TONY · WERNER TONY L · WERNER TONY LEE
20 granted patents·8 pending applications·308 citations·filing 1999–2024
95Inventor score
Top patents by PatentIndex Score
28 records- 0195US10620951B2Matrix multiplication acceleration of sparse matrices using column folding and squeezingINTEL CORP·Filed 2018·Granted Apr 14, 2020·35 cites·20 claims
- 0293US10482155B2Winograd algorithm on a matrix processing architectureINTEL CORP·Filed 2016·Granted Nov 19, 2019·12 cites·22 claims
- 0388US10228937B2Programmable matrix processing engineINTEL CORP·Filed 2016·Granted Mar 12, 2019·6 cites·21 claims
- 0486US9886377B2Pipelined convolutional operations for processing clustersINTEL CORP·Filed 2015·Granted Feb 6, 2018·7 cites·20 claims
- 0585US10949496B2Dimension shuffling using matrix processorsINTEL CORP·Filed 2016·Granted Mar 16, 2021·5 cites·20 claims
- 0683US9886418B2Matrix operands for linear algebra operationsINTEL CORP·Filed 2015·Granted Feb 6, 2018·5 cites·25 claims
- 0782US11687341B2Multi-variate strided read operations for accessing matrix operandsINTEL CORP·Filed 2019·Granted Jun 27, 2023·4 cites·25 claims
- 0881US7159102B2Branch control memoryRENESAS TECH CORP·Filed 2004·Granted Jan 2, 2007·27 cites·7 claims
- 0980US6397296B1Two-level instruction cache for embedded processorsHITACHI LTD·Filed 1999·Granted May 28, 2002·95 cites·26 claims
- 1079US6374348B1Prioritized pre-fetch/preload mechanism for loading and speculative preloading of candidate branch target instructionHITACHI LTD·Filed 2000·Granted Apr 16, 2002·18 cites·20 claims
- 1179US2024112006A1Deep learning hardwareINTEL CORP·Filed 2023·Application pending·0 cites
- 1277US10198401B2Max pooling in a matrix processing architectureINTEL CORP·Filed 2016·Granted Feb 5, 2019·3 cites·18 claims
- 1376US11748625B2Distributed convolution for neural networksINTEL CORP·Filed 2016·Granted Sep 5, 2023·3 cites·22 claims
- 1476US2023222331A1Deep learning hardwareINTEL CORP·Filed 2023·Application pending·0 cites
- 1575US10761757B2Apparatus and method for coherent, accelerated conversion between data representationsINTEL CORP·Filed 2018·Granted Sep 1, 2020·2 cites·24 claims
- 1675US6389531B1Indexing branch target instruction memory using target address generated by branch control instruction to reduce branch latencyHITACHI LTD·Filed 2000·Granted May 14, 2002·22 cites·16 claims
- 1774US10896039B2Programmable matrix processing engineINTEL CORP·Filed 2019·Granted Jan 19, 2021·2 cites·25 claims
- 1874US2025123843A1Multi-variate strided read operations for accessing matrix operandsINTEL CORP·Filed 2024·Application pending·0 cites
- 1972US2022245438A1Deep learning hardwareINTEL CORP·Filed 2022·Application pending·0 cites
- 2071US12229560B2Multi-variate strided read operations for accessing matrix operandsINTEL CORP·Filed 2023·Granted Feb 18, 2025·0 cites·18 claims
- 2166US2022121954A1Distributed convolution for neural networksINTEL CORP·Filed 2021·Application pending·0 cites
- 2262US6772325B1Processor architecture and operation for exploiting improved branch control instructionHITACHI LTD·Filed 1999·Granted Aug 3, 2004·33 cites·23 claims
- 2358US2019392297A1Deep learning hardwareINTEL CORP·Filed 2017·Application pending·0 cites
- 2453US2019171690A1Max pooling in a matrix processing architectureINTEL CORP·Filed 2019·Application pending·0 cites
- 2545US7408937B1Methods and apparatus for identifying a variable number of items first in sequence from a variable starting position which may be particularly useful by packet or other scheduling mechanismsCISCO TECH INC·Filed 2003·Granted Aug 5, 2008·0 cites·32 claims
- 2645US6449712B1Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructionsHITACHI LTD·Filed 1999·Granted Sep 10, 2002·18 cites·3 claims
- 2738US6393523B1Mechanism for invalidating instruction cache blocks in a pipeline processorHITACHI LTD·Filed 1999·Granted May 21, 2002·11 cites·14 claims
- 2832US2018188972A1Matrix storage using data shifting memoryINTEL CORP·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →