Inventor · disambiguated record
Suresh Uppal
Also filed as: UPPAL SURESH
12 granted patents·2 pending applications·444 citations·filing 2014–2018
88Inventor score
Files withGLOBALFOUNDRIES INC14
Top patents by PatentIndex Score
14 records- 0196US10106892B1Thermal oxide equivalent low temperature ALD oxide for dual purpose gate oxide and method for producing the sameGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 23, 2018·422 cites·15 claims
- 0282US9702926B2Methods, apparatus and system for screening process splits for technology developmentGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 11, 2017·4 cites·20 claims
- 0381US9372226B2Wafer test structures and methods of providing wafer test structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 21, 2016·5 cites·18 claims
- 0478US10181713B2Methods of post-process dispensation of plasma induced damage protection componentGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 15, 2019·6 cites·19 claims
- 0571US10012687B2Methods, apparatus and system for TDDB testingGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 3, 2018·2 cites·20 claims
- 0671US9460806B2Method for creating an OTPROM array possessing multi-bit capacity with TDDB stress reliability mechanismGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 4, 2016·2 cites·20 claims
- 0764US9599656B2Methods, apparatus and system for voltage ramp testingGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 21, 2017·1 cites·20 claims
- 0861US9916903B2OTPROM for post-process programming using selective breakdownGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 13, 2018·2 cites·12 claims
- 0959US10054630B2Methods, apparatus and system for screening process splits for technology developmentGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 21, 2018·0 cites·20 claims
- 1052US9324822B2Gate dielectric protection for transistorsGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 26, 2016·0 cites·16 claims
- 1150US9500703B2Semiconductor structure having test deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 22, 2016·0 cites·14 claims
- 1245US10147496B2OTPROM for post-process programming using selective breakdownGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 4, 2018·0 cites·20 claims
- 1345US2016204098A1Gate dielectric protection for transistorsGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 1440US2015377956A1Method and apparatus for inline device characterization and temperature profilingGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Suresh Uppal files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →