Inventor · disambiguated record
Marco Lepper
Also filed as: LEPPER MARCO
8 granted patents·3 pending applications·11 citations·filing 2005–2015
79Inventor score
Top patents by PatentIndex Score
11 records- 0173US8293605B2Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL)BAARS PETER·Filed 2011·Granted Oct 23, 2012·3 cites·14 claims
- 0270US9023696B2Method of forming contacts for devices with multiple stress linersBAARS PETER·Filed 2011·Granted May 5, 2015·3 cites·20 claims
- 0365US9590056B2Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layersGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 7, 2017·1 cites·20 claims
- 0464US7785935B2Manufacturing method for forming an integrated circuit device and corresponding integrated circuit deviceQIMONDA AG·Filed 2007·Granted Aug 31, 2010·3 cites·12 claims
- 0563US9023709B2Top corner rounding by implant-enhanced wet etchingGLOBALFOUNDRIES INC·Filed 2013·Granted May 5, 2015·1 cites·22 claims
- 0653US9269809B2Methods for forming protection layers on sidewalls of contact etch stop layersGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 23, 2016·0 cites·23 claims
- 0751US2015028431A1Mol insitu pt rework sequenceGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 0848US8883586B2Mol insitu Pt rework sequenceBAARS PETER·Filed 2011·Granted Nov 11, 2014·0 cites·12 claims
- 0940US8673696B2SOI semiconductor device comprising a substrate diode with reduced metal silicide leakageBAARS PETER·Filed 2012·Granted Mar 18, 2014·0 cites·17 claims
- 1040US2007077720A1Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structureINFINEON TECHNOLOGIES AG·Filed 2005·Application pending·0 cites
- 1140US2008150141A1Manufacturing method for an integrated semiconductor structure and corresponding semiconductor structureGRAF WERNER·Filed 2007·Application pending·0 cites
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