Mol insitu pt rework sequence

Abstract

The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O 2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.

What is claimed is: 
     
         1 . A device comprising:
 a semiconductor substrate;   gate electrodes on the semiconductor substrate; spacers on each side of each gate electrode; and platinum-containing nickel silicide on the substrate adjacent each spacer, wherein the device is at least 99% free from platinum residues.   
     
     
         2 . The device according to  claim 1 , further comprising nitride stress layers on and between the gate electrodes. 
     
     
         3 . The device according to  claim 1 , wherein the platinum-containing nickel silicide is formed by:
 sputter depositing a layer of nickel (Ni)/platinum (Pt) from a Ni/Pt target on the substrate;   performing a first RTA;   wet stripping unreacted Ni;   performing a second RTA;   stripping unreacted Pt from the annealed Ni/Pt layer;   treating the Pt stripped Ni/Pt layer with an oxygen plasma;   cleaning the Ni/Pt layer with an SPM/APM clean; and   stripping unreacted Pt from the cleaned Ni/Pt layer.   
     
     
         4 . The device according to  claim 3 , wherein the unreacted Pt is stripped by applying Aqua Regia. 
     
     
         5 . The device according to  claim 4 , wherein the spacers are etched and shaped concurrently with treating the Ni/Pt layer with the oxygen plasma. 
     
     
         6 . The device according to  claim 5 , wherein the Ni/Pt layer is treated with the oxygen plasma at a temperature less than 400° C. 
     
     
         7 . The device according to  claim 6 , wherein the Ni/Pt layer is treated with the oxygen plasma at a pressure of 350 mTorr to 8000 mTorr. 
     
     
         8 . The device according to  claim 6 , wherein unreacted Ni is wet stripped with a sulfuric acid-hydrogen peroxide mixture (SPM) at a temperature between 90° C. and 180° C. 
     
     
         9 . The device according to  claim 1 , wherein the gate electrodes comprise high K metal gate electrodes. 
     
     
         10 . A device comprising:
 a semiconductor substrate;   high K metal gate electrodes on the semiconductor substrate;   spacers on each side of each gate electrode;   platinum-containing nickel silicide on the substrate adjacent each spacer; and   nitride stress liners on the gate electrodes and on the platinum-containing nickel silicide,   wherein the device is at least 99% free from platinum residues and wherein the platinum-containing nickel silicide is formed by:
 sputter depositing a layer of nickel (Ni)/platinum (Pt) from a Ni/Pt target on the substrate; 
 performing a first rapid thermal anneal (RTA); 
 wet stripping unreacted Ni; 
 performing a second RTA; 
 stripping unreacted Pt from the annealed Ni/Pt layer; 
 treating the Pt stripped Ni/Pt layer with an oxygen plasma; 
 cleaning the Ni/Pt layer with an SPM/APM clean; and 
 stripping unreacted Pt from the cleaned Ni/Pt layer. 
   
     
     
         11 . The device according to  claim 10 , wherein the unreacted Pt is stripped by applying Aqua Regia. 
     
     
         12 . The device according to  claim 11 , wherein the spacers are etched and shaped concurrently with treating the Ni/Pt layer with the oxygen plasma. 
     
     
         13 . The device according to  claim 12 , wherein the Ni/Pt layer is treated with the oxygen plasma at a temperature less than 400° C. 
     
     
         14 . The device according to  claim 13 , wherein the Ni/Pt layer is treated with the oxygen plasma at a pressure of 350 mTorr to 8000 mTorr. 
     
     
         15 . The device according to  claim 13 , wherein unreacted Ni is wet stripped with a sulfuric acid-hydrogen peroxide mixture (SPM) at a temperature between 90° C. and 180° C. 
     
     
         16 . A device comprising:
 a plurality of semiconductor wafers;   at least one gate electrode on each semiconductor wafer;   platinum-containing nickel silicide on opposite sides of each gate electrode;   spacers separating the platinum-containing nickel silicide and each gate electrode; and   nitride stress liners on the gate electrodes and on the platinum-containing nickel silicide,   wherein the device is at least 99% free from platinum-containing residues.   
     
     
         17 . The device according to  claim 16 , wherein the gate electrodes comprise high K metal gate electrodes. 
     
     
         18 . The device according to  claim 16 , wherein the platinum-containing nickel silicide is formed by:
 sputter depositing a layer of nickel (Ni)/platinum (Pt) from a Ni/Pt target on each semiconductor wafer;   performing a first RTA;   wet stripping unreacted Ni;   performing a second RTA;   stripping unreacted Pt from the annealed Ni/Pt layer;   treating the Pt stripped Ni/Pt layer with an oxygen plasma;   cleaning the Ni/Pt layer with an SPM/APM clean; and   stripping unreacted Pt from the cleaned Ni/Pt layer.   
     
     
         19 . The device according to  claim 18 , wherein:
 the unreacted Pt is stripped by applying Aqua Regia; and   unreacted Ni is wet stripped with a sulfuric acid-hydrogen peroxide mixture (SPM) at a temperature between 90° C. and 180° C.   
     
     
         20 . The device according to  claim 19 , wherein:
 the Ni/Pt layer is treated with the oxygen plasma at a temperature less than 400° C. and at a pressure of 350 mTorr to 8000 mTorr; and   the spacers are etched and shaped concurrently with treating the Ni/Pt layer with the oxygen plasma.