Inventor · disambiguated record
Thomas E. Rosser
Also filed as: ROSSER THOMAS E · ROSSER THOMAS EDWARD
22 granted patents·3 pending applications·237 citations·filing 1991–2014
95Inventor score
Top patents by PatentIndex Score
25 records- 0185US9298872B2Apportioning synthesis effort for better timing closureIBM·Filed 2014·Granted Mar 29, 2016·7 cites·21 claims
- 0280US8443313B2Circuit design optimizationWARD SAMUEL I·Filed 2010·Granted May 14, 2013·7 cites·24 claims
- 0376US7979819B2Minterm tracing and reportingIBM·Filed 2009·Granted Jul 12, 2011·8 cites·15 claims
- 0475US7194394B2Method and apparatus for detecting and correcting inaccuracies in curve-fitted modelsIBM·Filed 2001·Granted Mar 20, 2007·23 cites·21 claims
- 0570US6526543B1Method, system, and computer program product for optimizing logic during synthesis of logic designsIBM·Filed 2001·Granted Feb 25, 2003·15 cites·20 claims
- 0668US6922818B2Method of power consumption reduction in clocked circuitsIBM·Filed 2001·Granted Jul 26, 2005·14 cites·27 claims
- 0767US7979732B2Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuitIBM·Filed 2007·Granted Jul 12, 2011·5 cites·17 claims
- 0866US8166439B2Techniques for selecting spares to implement a design change in an integrated circuitHOPKINS JEREMY T·Filed 2007·Granted Apr 24, 2012·4 cites·18 claims
- 0964US5524082ARedundancy removal using quasi-algebraic methodsIBM·Filed 1991·Granted Jun 4, 1996·40 cites·22 claims
- 1058US6654943B2Method, system, and computer program product for correcting anticipated problems related to global routingIBM·Filed 2001·Granted Nov 25, 2003·6 cites·63 claims
- 1156US6728944B2Method, system, and computer program product for improving wireability near dense clock netsINTENAT BUSINESS MACHINES CORP·Filed 2001·Granted Apr 27, 2004·5 cites·24 claims
- 1256US6460166B1System and method for restructuring of logic circuitryIBM·Filed 1998·Granted Oct 1, 2002·30 cites·8 claims
- 1351US7552040B2Method and system for modeling logical circuit blocks including transistor gate capacitance loading effectsIBM·Filed 2003·Granted Jun 23, 2009·2 cites·5 claims
- 1451US2008177517A1Techniques for calculating circuit block delay and transition times including transistor gate capacitance loading effectsDORFMAN BARRY LEE·Filed 2008·Application pending·0 cites
- 1547US5774369AComputer program product for enabling a computer to remove redundancies using quasi algebraic methodsIBM·Filed 1995·Granted Jun 30, 1998·21 cites·16 claims
- 1646US2010175038A1Techniques for Implementing an Engineering Change Order in an Integrated Circuit DesignINTERNATIONL BUISNESS MACHINES·Filed 2009·Application pending·0 cites
- 1745US6282695B1System and method for restructuring of logic circuitryIBM·Filed 1998·Granted Aug 28, 2001·16 cites·21 claims
- 1843US2008270955A1Method and apparatus for modifying existing circuit designISAKSON JOHN MACK·Filed 2007·Application pending·0 cites
- 1942US6339835B1Pseudo-anding in dynamic logic circuitsIBM·Filed 1999·Granted Jan 15, 2002·6 cites·28 claims
- 2041US8386230B2Circuit design optimizationIBM·Filed 2010·Granted Feb 26, 2013·0 cites·24 claims
- 2140US8572536B2Spare latch distributionANTONY GEORGE·Filed 2011·Granted Oct 29, 2013·0 cites·11 claims
- 2239US6018621AIdentifying an optimizable logic region in a logic networkIBM·Filed 1996·Granted Jan 25, 2000·11 cites·20 claims
- 2338US5903467ASelecting phase assignments for candidate nodes in a logic networkIBM·Filed 1996·Granted May 11, 1999·10 cites·16 claims
- 2434US6035110AIdentifying candidate nodes for phase assignment in a logic networkIBM·Filed 1996·Granted Mar 7, 2000·7 cites·8 claims
- 2531US8638120B2Programmable gate array as drivers for data ports of spare latchesJAITLY ASHISH·Filed 2011·Granted Jan 28, 2014·0 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →