Inventor · disambiguated record
Steven R. Soss
Also filed as: SOSS STEVEN · SOSS STEVEN R · SOSS STEVEN ROBERT
33 granted patents·6 pending applications·428 citations·filing 1997–2024
96Inventor score
Top patents by PatentIndex Score
39 records- 0199US10510620B1Work function metal patterning for N-P space between active nanostructuresGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 17, 2019·126 cites·6 claims
- 0299US10332803B1Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of formingGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 25, 2019·83 cites·20 claims
- 0397US10217846B1Vertical field effect transistor formation with critical dimension controlGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 26, 2019·21 cites·11 claims
- 0497US8048790B2Method for self-aligning a stop layer to a replacement gate for self-aligned contact integrationGLOBALFOUNDRIES INC·Filed 2009·Granted Nov 1, 2011·70 cites·12 claims
- 0595US11475941B2Non-volatile transistor embedded static random access memory (SRAM) cellGLOBALFOUNDRIES US INC·Filed 2020·Granted Oct 18, 2022·4 cites·20 claims
- 0695US11201152B2Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistorGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 14, 2021·12 cites·5 claims
- 0793US8581348B2Semiconductor device with transistor local interconnectsRASHED MAHBUB·Filed 2011·Granted Nov 12, 2013·20 cites·16 claims
- 0892US11444031B2Semiconductor device with transistor local interconnectsGLOBALFOUNDRIES US INC·Filed 2020·Granted Sep 13, 2022·2 cites·13 claims
- 0991US11145348B1Circuit structure and method for memory storage with memory cell and MRAM stackGLOBALFOUNDRIES US INC·Filed 2020·Granted Oct 12, 2021·3 cites·19 claims
- 1091US9355910B2Semiconductor device with transistor local interconnectsRASHED MAHBUB·Filed 2011·Granted May 31, 2016·10 cites·7 claims
- 1190US10418368B1Buried local interconnect in source/drain regionGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 17, 2019·7 cites·20 claims
- 1288US6869892B1Method of oxidizing work pieces and oxidation systemTOKYO ELECTRON LTD·Filed 2004·Granted Mar 22, 2005·43 cites·9 claims
- 1388US2025038111A1Semiconductor device with transistor local interconnectsGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 1485US10833018B2Semiconductor device with transistor local interconnectsGLOBALFOUNDRIES INC·Filed 2019·Granted Nov 10, 2020·2 cites·20 claims
- 1584US11315949B2Charge-trapping sidewall spacer-type non-volatile memory device and methodGLOBALFOUNDRIES DRESDEN MOD 1·Filed 2020·Granted Apr 26, 2022·2 cites·20 claims
- 1684US8940634B2Overlapping contacts for semiconductor deviceENGEL BRETT H·Filed 2011·Granted Jan 27, 2015·8 cites·12 claims
- 1783US10964367B1MRAM device comprising random access memory (RAM) and embedded read only memory (ROM)GLOBALFOUNDRIES US INC·Filed 2020·Granted Mar 30, 2021·2 cites·10 claims
- 1879US12148702B2Semiconductor device with transistor local interconnectsGLOBALFOUNDRIES US INC·Filed 2022·Granted Nov 19, 2024·0 cites·20 claims
- 1979US7183162B1Method of forming non-volatile memory cell using sacrificial pillar spacers and non-volatile memory cell formed according to the methodINTEL CORP·Filed 2005·Granted Feb 27, 2007·8 cites·14 claims
- 2071US10446451B1Method for forming replacement gate structures for vertical transistorsGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 15, 2019·1 cites·20 claims
- 2170US11004509B1Circuit structure and memory circuit with resistive memory elements, and related methodsGLOBALFOUNDRIES US INC·Filed 2019·Granted May 11, 2021·2 cites·19 claims
- 2262US10629500B2Product that includes a plurality of vertical transistors with a shared conductive gate plugGLOBALFOUNDRIES INC·Filed 2019·Granted Apr 21, 2020·0 cites·20 claims
- 2359US8071457B2Low capacitance precision resistorSOSS STEVEN R·Filed 2010·Granted Dec 6, 2011·1 cites·12 claims
- 2457US2016268204A1Semiconductor device with transistor local interconnectsGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 2555US9048171B2Method to dynamically tune precision resistanceGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 2, 2015·0 cites·20 claims
- 2654US11217533B2Semiconductor device with metal structure under an active layerGLOBALFOUNDRIES US INC·Filed 2020·Granted Jan 4, 2022·0 cites·20 claims
- 2752US11349071B2Memory device and a method for forming the memory deviceGLOBALFOUNDRIES SG PTE LTD·Filed 2019·Granted May 31, 2022·0 cites·19 claims
- 2849US2013241070A1Overlapping contacts for semiconductor deviceIBM·Filed 2013·Application pending·0 cites
- 2948US8853045B2Low capacitance precision resistorSOSS STEVEN R·Filed 2011·Granted Oct 7, 2014·0 cites·18 claims
- 3046US10559686B2Methods of forming gate contact over active region for vertical FinFET, and structures formed therebyGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 11, 2020·0 cites·20 claims
- 3145US8709882B2Method to dynamically tune precision resistanceSOSS STEVEN R·Filed 2010·Granted Apr 29, 2014·0 cites·8 claims
- 3244US11101348B2Nanosheet field effect transistor with spacers between sheetsGLOBALFOUNDRIES US INC·Filed 2018·Granted Aug 24, 2021·0 cites·15 claims
- 3343US2012068234A1Method for self-aligning a stop layer to a replacement gate for self-aligned contact integrationSOSS STEVEN R·Filed 2011·Application pending·0 cites
- 3442US10699942B2Vertical-transport field-effect transistors having gate contacts located over the active regionGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 30, 2020·0 cites·7 claims
- 3541US10658243B2Method for forming replacement metal gate and related structuresGLOBALFOUNDRIES INC·Filed 2018·Granted May 19, 2020·0 cites·16 claims
- 3640US9625557B2Work function calibration of a non-contact voltage sensorSTEELE M BRANDON·Filed 2014·Granted Apr 18, 2017·0 cites·10 claims
- 3740US2007114592A1Method of forming non-volatile memory cell using spacers and non-volatile memory cell formed according to the methodINTEL CORP·Filed 2005·Application pending·0 cites
- 3839US2022068340A1Non-volatile static random access memoryGLOBALFOUNDRIES US INC·Filed 2020·Application pending·0 cites
- 3929US5956604AOhmic contact to Gallium Arsenide using epitaxially deposited Cobalt DigermanideUS ARMY·Filed 1997·Granted Sep 21, 1999·1 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →