Inventor · disambiguated record
Deniz E. Civay
Also filed as: CIVAY DENIZ · CIVAY DENIZ E · CIVAY DENIZ ELIZABETH
15 granted patents·1 pending application·27 citations·filing 2010–2024
88Inventor score
Top patents by PatentIndex Score
16 records- 0189US9397004B2Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openingsGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 19, 2016·10 cites·14 claims
- 0281US8758802B2Methods of inhibiting cataracts and presbyopiaMUTHUKUMAR MURUGAPPAN·Filed 2010·Granted Jun 24, 2014·5 cites·16 claims
- 0376US9754829B2Self-aligned conductive polymer pattern placement error compensation layerGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 5, 2017·3 cites·18 claims
- 0474US10262941B2Devices and methods for forming cross coupled contactsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 16, 2019·2 cites·13 claims
- 0571US9530689B2Methods for fabricating integrated circuits using multi-patterning processesGLOBALFOUNDRIES INC·Filed 2015·Granted Dec 27, 2016·2 cites·12 claims
- 0667US10552567B2Automated redesign of integrated circuits using relaxed spacing rulesGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 4, 2020·2 cites·20 claims
- 0765US9633942B1Conductively doped polymer pattern placement error compensation layerGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 25, 2017·1 cites·17 claims
- 0865US9283237B2Methods of inhibiting presbyopiaUNIV MASSACHUSETTS·Filed 2014·Granted Mar 15, 2016·0 cites·12 claims
- 0963US9397012B2Test pattern for feature cross-sectioningGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 19, 2016·1 cites·10 claims
- 1061US9275896B2Methods for fabricating integrated circuits using directed self-assemblyGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 1, 2016·1 cites·13 claims
- 1158US2025258341A1Optical coupling between stacked chipsGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 1256US10186524B2Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regionsGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 22, 2019·0 cites·20 claims
- 1350US9941301B1Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regionsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 10, 2018·0 cites·12 claims
- 1442US9748176B2Pattern placement error compensation layer in via openingGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 29, 2017·0 cites·18 claims
- 1541US9704807B2Pattern placement error compensation layerGLOBALFOUNDRIES INC·Filed 2015·Granted Jul 11, 2017·0 cites·6 claims
- 1632US9576097B1Methods for circuit pattern layout decompositionGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 21, 2017·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →