Inventor · disambiguated record
Igor Vikhliantsev
Also filed as: VIKHLIANTSEV IGOR · VIKHLIANTSEV IGOR A
26 granted patents·2 pending applications·156 citations·filing 2001–2012
95Inventor score
Top patents by PatentIndex Score
28 records- 0188US7913149B2Low complexity LDPC encoding algorithmLSI CORP·Filed 2006·Granted Mar 22, 2011·16 cites·4 claims
- 0281US9024657B2Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smallerEASIC CORP·Filed 2012·Granted May 5, 2015·9 cites·18 claims
- 0380US6941533B2Clock tree synthesis with skew for memory devicesLSI LOGIC CORP·Filed 2002·Granted Sep 6, 2005·28 cites·22 claims
- 0479US8151160B1Configurable low-density parity-check decoder for LDPC codes of arbitrary block size and method of configuring the sameANDREEV ALEXANDER E·Filed 2008·Granted Apr 3, 2012·11 cites·19 claims
- 0577US7934139B2Parallel LDPC decoderLSI CORP·Filed 2006·Granted Apr 26, 2011·9 cites·2 claims
- 0677US6941494B1Built-in test for multiple memory circuitsLSI LOGIC CORP·Filed 2001·Granted Sep 6, 2005·24 cites·22 claims
- 0768US7584442B2Method and apparatus for generating memory models and timing databaseLSI CORP·Filed 2005·Granted Sep 1, 2009·3 cites·9 claims
- 0868US7072922B2Integrated circuit and process for identifying minimum or maximum input value among plural inputsLSI LOGIC CORP·Filed 2002·Granted Jul 4, 2006·13 cites·20 claims
- 0964US8245168B2Method and apparatus for generating memory models and timing databaseANDREEV ALEXANDRE·Filed 2009·Granted Aug 14, 2012·2 cites·11 claims
- 1062US6507939B1Net delay optimization with ramptime violation removalLSI LOGIC CORP·Filed 2001·Granted Jan 14, 2003·8 cites·18 claims
- 1161US7050582B1Pseudo-random one-to-one circuit synthesisLSI LOGIC CORP·Filed 2001·Granted May 23, 2006·6 cites·18 claims
- 1259US6848094B2Netlist redundancy detection and global simplificationLSI LOGIC CORP·Filed 2002·Granted Jan 25, 2005·6 cites·20 claims
- 1358US7036102B2Process and apparatus for placement of cells in an IC during floorplan creationLSI LOGIC CORP·Filed 2003·Granted Apr 25, 2006·5 cites·17 claims
- 1457US7667494B2Methods and apparatus for fast unbalanced pipeline architectureLSI CORP·Filed 2008·Granted Feb 23, 2010·1 cites·20 claims
- 1555US8035537B2Methods and apparatus for programmable decoding of a plurality of code typesLSI CORP·Filed 2008·Granted Oct 11, 2011·3 cites·18 claims
- 1655US7062726B2Method for generating tech-library for logic functionLSI LOGIC CORP·Filed 2003·Granted Jun 13, 2006·4 cites·24 claims
- 1754US7210113B2Process and apparatus for placing cells in an IC floorplanLSI LOGIC CORP·Filed 2004·Granted Apr 24, 2007·3 cites·18 claims
- 1853US7065606B2Controller architecture for memory mappingLSI LOGIC CORP·Filed 2003·Granted Jun 20, 2006·2 cites·16 claims
- 1952US8566769B2Method and apparatus for generating memory models and timing databaseANDREEV ALEXANDRE·Filed 2012·Granted Oct 22, 2013·0 cites·13 claims
- 2052US7822099B2Digital Gaussian noise simulatorLSI CORP·Filed 2007·Granted Oct 26, 2010·0 cites·13 claims
- 2150US7155688B2Memory generation and placementLSI LOGIC CORP·Filed 2004·Granted Dec 26, 2006·1 cites·5 claims
- 2247US7207026B2Memory tiling architectureLSI LOGIC CORP·Filed 2004·Granted Apr 17, 2007·0 cites·4 claims
- 2346US7263470B2Digital gaussian noise simulatorLSI CORP·Filed 2003·Granted Aug 28, 2007·0 cites·12 claims
- 2445US8347167B2Circuits for implementing parity computation in a parallel architecture LDPC decoderLSI CORP·Filed 2008·Granted Jan 1, 2013·2 cites·4 claims
- 2540US2011173510A1Parallel LDPC DecoderLSI CORP·Filed 2011·Application pending·0 cites
- 2640US2011099454A1Low Complexity LDPC Encoding AlgorithmLSI CORP·Filed 2011·Application pending·0 cites
- 2736US7739471B2High performance tiling for RRAM memoryLSI CORP·Filed 2005·Granted Jun 15, 2010·0 cites·7 claims
- 2835US7313660B2Data stream frequency reduction and/or phase shiftLSI CORP·Filed 2003·Granted Dec 25, 2007·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →