US2011173510A1PendingUtilityA1
Parallel LDPC Decoder
Est. expiryDec 1, 2026(~0.3 yrs left)· nominal 20-yr term from priority
H03M 13/114H03M 13/116H03M 13/1137
40
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Claims
Abstract
An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.
Claims
exact text as granted — not AI-modified1 . In an LDPC decoder implementing an iterative message-passing algorithm, the improvement comprising a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.
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