Inventor · disambiguated record
Miao-Chun Lin
Also filed as: LIN MIAO-CHUN
5 granted patents·3 pending applications·52 citations·filing 2005–2007
78Inventor score
Top patents by PatentIndex Score
8 records- 0190US7192878B2Method for removing post-etch residue from wafer surfaceUNITED MICROELECTRONICS CORP·Filed 2005·Granted Mar 20, 2007·20 cites·20 claims
- 0289US7378343B2Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon contentUNITED MICROELECTRONICS CORP·Filed 2005·Granted May 27, 2008·20 cites·20 claims
- 0374US7628866B2Method of cleaning wafer after etching processUNITED MICROELECTRONICS CORP·Filed 2006·Granted Dec 8, 2009·7 cites·14 claims
- 0470US7214612B2Dual damascene structure and fabrication thereofUNITED MICROELECTRONICS CORP·Filed 2005·Granted May 8, 2007·5 cites·8 claims
- 0548US2007125750A1Method for removing post-etch residue from wafer surfaceWENG CHENG-MING·Filed 2007·Application pending·0 cites
- 0645US2007080386A1Dual damascene structureUNITED MICROELECTRONICS CORP·Filed 2006·Application pending·0 cites
- 0740US7687446B2Method of removing residue left after plasma processUNITED MICROELECTRONICS CORP·Filed 2006·Granted Mar 30, 2010·0 cites·14 claims
- 0836US2007052107A1Multi-layered structure and fabricating method thereof and dual damascene structure, interconnect structure and capacitorWENG CHENG-MING·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →