Inventor · disambiguated record
Peter Hsu
Also filed as: HSU PETER · HSU PETER Y · HSU PETER Y T · HSU PETER YAN-TEK
20 granted patents·1 pending application·1,624 citations·filing 1993–2010
97Inventor score
Technology areasG06F
Files withMIPS TECH INC9SILICON GRAPHICS INC7NINTENDO CO LTD2MAHER MONIER1SILICON GRAPHICS COMPUTER SYST1
Top patents by PatentIndex Score
21 records- 0197US5933650AAlignment and ordering of vector elements for single instruction multiple data processingMIPS TECH INC·Filed 1997·Granted Aug 3, 1999·352 cites·44 claims
- 0295US5864703AMethod for providing extended precision in SIMD vector arithmetic operationsMIPS TECH INC·Filed 1997·Granted Jan 26, 1999·204 cites·40 claims
- 0393US8074058B2Providing extended precision in SIMD vector arithmetic operationsVAN HOOK TIMOTHY J·Filed 2009·Granted Dec 6, 2011·24 cites·20 claims
- 0492US7197625B1Alignment and ordering of vector elements for single instruction multiple data processingMIPS TECH INC·Filed 2000·Granted Mar 27, 2007·61 cites·18 claims
- 0590US6691221B2Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel executionMIPS TECH INC·Filed 2001·Granted Feb 10, 2004·52 cites·39 claims
- 0689US5526504AVariable page size translation lookaside bufferSILICON GRAPHICS INC·Filed 1993·Granted Jun 11, 1996·166 cites·8 claims
- 0786US7793077B2Alignment and ordering of vector elements for single instruction multiple data processingMIPS TECH INC·Filed 2007·Granted Sep 7, 2010·12 cites·14 claims
- 0886US6681296B2Method and apparatus for software management of on-chip cacheNINTENDO CO LTD·Filed 2001·Granted Jan 20, 2004·39 cites·12 claims
- 0985US6859862B1Method and apparatus for software management of on-chip cacheNINTENDO CO LTD·Filed 2000·Granted Feb 22, 2005·37 cites·2 claims
- 1084US8180998B1System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operationsMAHER MONIER·Filed 2008·Granted May 15, 2012·20 cites·18 claims
- 1182US7546443B2Providing extended precision in SIMD vector arithmetic operationsMIPS TECH INC·Filed 2006·Granted Jun 9, 2009·8 cites·20 claims
- 1282US5604909AApparatus for processing instructions in a computing systemSILICON GRAPHICS COMPUTER SYST·Filed 1993·Granted Feb 18, 1997·79 cites·19 claims
- 1382US5572704ASystem and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemesSILICON GRAPHICS INC·Filed 1993·Granted Nov 5, 1996·91 cites·14 claims
- 1481US5740402AConflict resolution in interleaved memory systems with multiple parallel accessesSILICON GRAPHICS INC·Filed 1995·Granted Apr 14, 1998·117 cites·7 claims
- 1579US5510934AMemory system including local and global caches for storing floating point and integer dataSILICON GRAPHICS INC·Filed 1993·Granted Apr 23, 1996·87 cites·5 claims
- 1678US5954815AInvalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target addressSILICON GRAPHICS INC·Filed 1997·Granted Sep 21, 1999·65 cites·7 claims
- 1778US5632025AMethod for preventing multi-level cache system deadlock in a multi-processor systemSILICON GRAPHICS INC·Filed 1996·Granted May 20, 1997·82 cites·3 claims
- 1872US6247124B1Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructionsMIPS TECH INC·Filed 1999·Granted Jun 12, 2001·47 cites·23 claims
- 1971US5537538ADebug mode for a superscalar RISC processorSILICON GRAPHICS INC·Filed 1993·Granted Jul 16, 1996·58 cites·4 claims
- 2057US7159100B2Method for providing extended precision in SIMD vector arithmetic operationsMIPS TECH INC·Filed 1998·Granted Jan 2, 2007·23 cites·8 claims
- 2150US2011055497A1Alignment and Ordering of Vector Elements for Single Instruction Multiple Data ProcessingMIPS TECH INC·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →