Inventor · disambiguated record
Fadi Maamari
Also filed as: MAAMARI FADI
14 granted patents·1 pending application·154 citations·filing 1992–2023
91Inventor score
Top patents by PatentIndex Score
15 records- 0194US6510534B1Method and apparatus for testing high performance circuitsLOGICVISION INC·Filed 2000·Granted Jan 21, 2003·82 cites·44 claims
- 0293US11288428B1Integrated circuit design modification for localization of scan chain defectsSYNOPSYS INC·Filed 2020·Granted Mar 29, 2022·3 cites·20 claims
- 0392US12282063B1Scan chain formation for improving chain resolutionSYNOPSYS INC·Filed 2023·Granted Apr 22, 2025·1 cites·20 claims
- 0489US11829692B1Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QOR)SYNOPSYS INC·Filed 2021·Granted Nov 28, 2023·4 cites·16 claims
- 0585US8533647B1Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) designATRENTA INC·Filed 2012·Granted Sep 10, 2013·13 cites·12 claims
- 0676US12333227B1Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QoR)SYNOPSYS INC·Filed 2023·Granted Jun 17, 2025·0 cites·20 claims
- 0774US6457161B1Method and program product for modeling circuits with latch based designFiled 2001·Granted Sep 24, 2002·22 cites·25 claims
- 0859US7424656B2Clocking methodology for at-speed testing of scan circuits with synchronous clocksLOGICVISION INC·Filed 2005·Granted Sep 9, 2008·3 cites·21 claims
- 0958US8788993B2Computer system for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) designATRENTA INC·Filed 2013·Granted Jul 22, 2014·1 cites·12 claims
- 1058US7191374B2Method of and program product for performing gate-level diagnosis of failing vectorsLOGICVISION INC·Filed 2003·Granted Mar 13, 2007·9 cites·35 claims
- 1152US11842134B2Automated determinaton of failure mode distributionSYNOPSYS INC·Filed 2021·Granted Dec 12, 2023·0 cites·20 claims
- 1248US6883134B2Method and program product for detecting bus conflict and floating bus conditions in circuit designsLOGICVISION INC·Filed 2001·Granted Apr 19, 2005·2 cites·76 claims
- 1342US5418792AMethod for the speedup of test vector generation for digital circuitsAT & T CORP·Filed 1992·Granted May 23, 1995·10 cites·10 claims
- 1437US2005273683A1Insertion of embedded test in RTL to GDSII flowLOGICVISION INC·Filed 2005·Application pending·0 cites
- 1531US5420871AMethod for maintaining bus integrity during testingAT & T CORP·Filed 1994·Granted May 30, 1995·4 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →