Inventor · disambiguated record
Troy L. Graves-Abe
Also filed as: GRAVES-ABE TROY · GRAVES-ABE TROY L · GRAVES-ABE TROY LAWRENCE
29 granted patents·4 pending applications·84 citations·filing 2004–2019
95Inventor score
Top patents by PatentIndex Score
33 records- 0192US8791009B2Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon viaFAROOQ MUKTA G·Filed 2011·Granted Jul 29, 2014·11 cites·9 claims
- 0289US8476168B2Non-conformal hardmask deposition for through silicon etchGRAVES-ABE TROY L·Filed 2011·Granted Jul 2, 2013·14 cites·16 claims
- 0388US8691691B2TSV pillar as an interconnecting structureFAROOQ MUKTA G·Filed 2011·Granted Apr 8, 2014·10 cites·16 claims
- 0487US8546961B2Alignment marks to enable 3D integrationFAROOQ MUKTA G·Filed 2011·Granted Oct 1, 2013·9 cites·19 claims
- 0582US9214435B2Via structure for three-dimensional circuit integrationFAROOQ MUKTA G·Filed 2012·Granted Dec 15, 2015·5 cites·17 claims
- 0682US8956973B2Bottom-up plating of through-substrate viasFAROOQ MUKTA G·Filed 2012·Granted Feb 17, 2015·5 cites·9 claims
- 0782US8951906B2Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon viaIBM·Filed 2014·Granted Feb 10, 2015·4 cites·4 claims
- 0882US8853857B23-D integration using multi stage viasFAROOQ MUKTA G·Filed 2011·Granted Oct 7, 2014·5 cites·11 claims
- 0978US9886193B2Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integrationIBM·Filed 2015·Granted Feb 6, 2018·2 cites·25 claims
- 1078US8791005B2Sidewalls of electroplated copper interconnectsFAROOQ MUKTA G·Filed 2012·Granted Jul 29, 2014·3 cites·8 claims
- 1173US9640514B1Wafer bonding using boron and nitrogen based bonding stackGLOBALFOUNDRIES INC·Filed 2016·Granted May 2, 2017·2 cites·17 claims
- 1273US8889542B2Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon viaIBM·Filed 2014·Granted Nov 18, 2014·2 cites·8 claims
- 1370US9263324B23-D integration using multi stage viasGLOBALFOUNDRIES INC·Filed 2013·Granted Feb 16, 2016·2 cites·6 claims
- 1469US8927427B2Anticipatory implant for TSVIBM·Filed 2013·Granted Jan 6, 2015·2 cites·20 claims
- 1569US8907494B2Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structuresIBM·Filed 2013·Granted Dec 9, 2014·2 cites·15 claims
- 1666US9055703B2Sidewalls of electroplated copper interconnectsIBM·Filed 2013·Granted Jun 9, 2015·1 cites·14 claims
- 1765US10613754B2Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integrationIBM·Filed 2019·Granted Apr 7, 2020·0 cites·20 claims
- 1864US9252133B2Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 2, 2016·1 cites·5 claims
- 1962US8138041B2In-situ silicon cap for metal gate electrodeCHUDZIK MICHAEL P·Filed 2008·Granted Mar 20, 2012·1 cites·9 claims
- 2057US10503402B2Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integrationIBM·Filed 2017·Granted Dec 10, 2019·0 cites·20 claims
- 2157US9060457B2Sidewalls of electroplated copper interconnectsIBM·Filed 2013·Granted Jun 16, 2015·0 cites·17 claims
- 2257US9040407B2Sidewalls of electroplated copper interconnectsIBM·Filed 2013·Granted May 26, 2015·0 cites·7 claims
- 2355US9257336B2Bottom-up plating of through-substrate viasGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 9, 2016·0 cites·12 claims
- 2453US7569416B2Forming closely spaced electrodesALCATEL LUCENT USA INC·Filed 2006·Granted Aug 4, 2009·0 cites·14 claims
- 2553US2015035169A1Via structure for three-dimensional circuit integrationIBM·Filed 2014·Application pending·0 cites
- 2652US7119356B2Forming closely spaced electrodesUNIV PRINCETON·Filed 2004·Granted Oct 10, 2006·3 cites·11 claims
- 2752US2015097274A1Through-silicon via structure and method for improving beol dielectric performanceIBM·Filed 2014·Application pending·0 cites
- 2850US9476927B2Structure and method to determine through silicon via build integrityGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 25, 2016·0 cites·12 claims
- 2949US2015069608A1Through-silicon via structure and method for improving beol dielectric performanceIBM·Filed 2013·Application pending·0 cites
- 3045US10296698B2Forming multi-sized through-silicon-via (TSV) structuresGLOBALFOUNDRIES INC·Filed 2016·Granted May 21, 2019·0 cites·19 claims
- 3143US10170337B2Implant after through-silicon via (TSV) etch to getter mobile ionsIBM·Filed 2016·Granted Jan 1, 2019·0 cites·14 claims
- 3243US8975910B2Through-silicon-via with sacrificial dielectric lineGRAVES-ABE TROY L·Filed 2012·Granted Mar 10, 2015·0 cites·24 claims
- 3341US2014061915A1Prevention of thru-substrate via pistoning using highly doped copper alloy seed layerCOLLINS CHRISTOPHER N·Filed 2012·Application pending·0 cites
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