Inventor · disambiguated record
Zigmund Ramirez Camacho
Also filed as: CAMACHO JR ZIGMUND RAMIREZ · CAMACHO ZIGMUND R · CAMACHO ZIGMUND RAMIREZ
220 granted patents·13 pending applications·1,719 citations·filing 2003–2020
99Inventor score
Files withSTATS CHIPPAC LTD72CAMACHO ZIGMUND RAMIREZ71CAMACHO ZIGMUND R24BATHAN HENRY DESCALZO17TAY LIONEL CHIEN HUI11
Top patents by PatentIndex Score
233 records- 0199US7517733B2Leadframe design for QFN package with top terminal leadsSTATS CHIPPAC LTD·Filed 2007·Granted Apr 14, 2009·125 cites·22 claims
- 0298US9177832B2Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnectCAMACHO ZIGMUND R·Filed 2011·Granted Nov 3, 2015·48 cites·28 claims
- 0398US8993376B2Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor dieCAMACHO ZIGMUND R·Filed 2011·Granted Mar 31, 2015·52 cites·23 claims
- 0498US8940636B2Through hole vias at saw streets including protrusions or recesses for interconnectionPAGAILA REZA A·Filed 2011·Granted Jan 27, 2015·39 cites·21 claims
- 0598US8420447B2Integrated circuit packaging system with flipchip leadframe and method of manufacture thereofTAY LIONEL CHIEN HUI·Filed 2011·Granted Apr 16, 2013·80 cites·20 claims
- 0698US8409922B2Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnectCAMACHO ZIGMUND R·Filed 2010·Granted Apr 2, 2013·58 cites·31 claims
- 0798US8076184B1Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor dieCAMACHO ZIGMUND R·Filed 2010·Granted Dec 13, 2011·43 cites·12 claims
- 0897US9006031B2Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumpsCAMACHO ZIGMUND R·Filed 2011·Granted Apr 14, 2015·40 cites·24 claims
- 0997US8021907B2Method and apparatus for thermally enhanced semiconductor packageSTATS CHIPPAC LTD·Filed 2008·Granted Sep 20, 2011·43 cites·18 claims
- 1097US7915716B2Integrated circuit package system with leadframe arraySTATS CHIPPAC LTD·Filed 2007·Granted Mar 29, 2011·62 cites·18 claims
- 1197US7851246B2Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the deviceSTATS CHIPPAC LTD·Filed 2007·Granted Dec 14, 2010·40 cites·18 claims
- 1296US8241956B2Semiconductor device and method of forming wafer level multi-row etched lead packageCAMACHO ZIGMUND R·Filed 2010·Granted Aug 14, 2012·25 cites·20 claims
- 1396US7977579B2Multiple flip-chip integrated circuit package systemSTATS CHIPPAC LTD·Filed 2006·Granted Jul 12, 2011·40 cites·20 claims
- 1495US7888181B2Method of forming a wafer level package with RDL interconnection over encapsulant between bump and semiconductor dieSTATS CHIPPAC LTD·Filed 2008·Granted Feb 15, 2011·25 cites·23 claims
- 1594US8884418B2Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumpsCAMACHO ZIGMUND R·Filed 2012·Granted Nov 11, 2014·15 cites·25 claims
- 1694US7400049B2Integrated circuit package system with heat sinkSTATS CHIPPAC LTD·Filed 2006·Granted Jul 15, 2008·34 cites·12 claims
- 1793US7964450B2Wirebondless wafer level package with plated bumps and interconnectsSTATS CHIPPAC LTD·Filed 2008·Granted Jun 21, 2011·22 cites·36 claims
- 1892US9330994B2Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuringSTATS CHIPPAC LTD·Filed 2014·Granted May 3, 2016·22 cites·21 claims
- 1992US9331003B1Integrated circuit packaging system with pre-molded leadframe and method of manufacture thereofCAMACHO ZIGMUND RAMIREZ·Filed 2014·Granted May 3, 2016·15 cites·19 claims
- 2092US8389333B2Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around dieCAMACHO ZIGMUND R·Filed 2011·Granted Mar 5, 2013·12 cites·25 claims
- 2192US8377750B2Integrated circuit packaging system with multiple row leads and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2010·Granted Feb 19, 2013·14 cites·17 claims
- 2292US8035207B2Stackable integrated circuit package system with recessSTATS CHIPPAC LTD·Filed 2006·Granted Oct 11, 2011·23 cites·20 claims
- 2391US9406531B1Integrated circuit packaging system with photoimagable dielectric-defined trace and method of manufacture thereofCAMACHO ZIGMUND RAMIREZ·Filed 2014·Granted Aug 2, 2016·11 cites·9 claims
- 2491US8735224B2Integrated circuit packaging system with routed circuit lead array and method of manufacture thereofDO BYUNG TAI·Filed 2011·Granted May 27, 2014·10 cites·10 claims
- 2591US7790576B2Semiconductor device and method of forming through hole vias in die extension region around periphery of dieSTATS CHIPPAC LTD·Filed 2007·Granted Sep 7, 2010·15 cites·18 claims
- 2690US7868471B2Integrated circuit package-in-package system with leadsSTATS CHIPPAC LTD·Filed 2007·Granted Jan 11, 2011·22 cites·8 claims
- 2790US7838395B2Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the sameSTATS CHIPPAC LTD·Filed 2007·Granted Nov 23, 2010·15 cites·24 claims
- 2890US7691674B1Integrated circuit packaging system with stacked device and method of manufacturing thereofSTATS CHIPPAC LTD·Filed 2009·Granted Apr 6, 2010·19 cites·20 claims
- 2990US7563647B2Integrated circuit package system with interconnect supportSTATS CHIPPAC LTD·Filed 2006·Granted Jul 21, 2009·17 cites·14 claims
- 3089US8866275B2Leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnectSTATS CHIPPAC LTD·Filed 2013·Granted Oct 21, 2014·8 cites·25 claims
- 3189US8193037B1Integrated circuit packaging system with pad connection and method of manufacture thereofBATHAN HENRY DESCALZO·Filed 2010·Granted Jun 5, 2012·11 cites·11 claims
- 3289US8097943B2Semiconductor device and method of forming wafer level ground plane and power ringBADAKERE GURUPRASAD G·Filed 2010·Granted Jan 17, 2012·11 cites·24 claims
- 3388US8110440B2Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structureBATHAN HENRY D·Filed 2009·Granted Feb 7, 2012·14 cites·31 claims
- 3488US8106499B2Integrated circuit packaging system with a dual substrate package and method of manufacture thereofCAMACHO ZIGMUND RAMIREZ·Filed 2009·Granted Jan 31, 2012·15 cites·20 claims
- 3588US7977780B2Multi-layer package-on-package systemSTATS CHIPPAC LTD·Filed 2008·Granted Jul 12, 2011·16 cites·20 claims
- 3687US9922955B2Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSPCAMACHO ZIGMUND R·Filed 2010·Granted Mar 20, 2018·9 cites·17 claims
- 3786US8334584B2Integrated circuit packaging system with quad flat no-lead package and method of manufacture thereofCAMACHO ZIGMUND RAMIREZ·Filed 2009·Granted Dec 18, 2012·13 cites·20 claims
- 3886US8120149B2Integrated circuit package systemCAMACHO ZIGMUND RAMIREZ·Filed 2006·Granted Feb 21, 2012·14 cites·20 claims
- 3986US8105915B2Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layersCAMACHO ZIGMUND R·Filed 2009·Granted Jan 31, 2012·12 cites·25 claims
- 4085US8120156B2Integrated circuit package system with die on base packageCAMACHO ZIGMUND RAMIREZ·Filed 2006·Granted Feb 21, 2012·13 cites·20 claims
- 4184US8354742B2Method and apparatus for a package having multiple stacked dieSTATS CHIPPAC LTD·Filed 2008·Granted Jan 15, 2013·11 cites·30 claims
- 4284US8227910B2Apparatus for thermally enhanced semiconductor packagePAGAILA REZA A·Filed 2011·Granted Jul 24, 2012·5 cites·22 claims
- 4384US8043894B2Integrated circuit package system with redistribution layerSTATS CHIPPAC LTD·Filed 2008·Granted Oct 25, 2011·11 cites·20 claims
- 4484US7901996B2Integrated circuit package system with interconnection support and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2009·Granted Mar 8, 2011·9 cites·14 claims
- 4584US7714419B2Integrated circuit package system with shieldingSTATS CHIPPAC LTD·Filed 2007·Granted May 11, 2010·13 cites·17 claims
- 4684US6833287B1System for semiconductor package with stacked diesST ASSEMBLY TEST SERVICES INC·Filed 2003·Granted Dec 21, 2004·56 cites·20 claims
- 4783US9355983B1Integrated circuit packaging system with interposer structure and method of manufacture thereofCAMACHO ZIGMUND RAMIREZ·Filed 2014·Granted May 31, 2016·5 cites·15 claims
- 4883US8022539B2Integrated circuit packaging system with increased connectivity and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2008·Granted Sep 20, 2011·9 cites·7 claims
- 4983US7919850B2Integrated circuit packaging system with exposed terminal interconnects and method of manufacturing thereofSTATS CHIPPAC LTD·Filed 2008·Granted Apr 5, 2011·12 cites·20 claims
- 5083US7750451B2Multi-chip package system with multiple substratesSTATS CHIPPAC LTD·Filed 2007·Granted Jul 6, 2010·11 cites·20 claims
Showing the top 50 of 233 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →