Inventor · disambiguated record
Tonglong Zhang
Also filed as: ZHANG TONGLONG
13 granted patents·6 pending applications·252 citations·filing 2000–2022
93Inventor score
Top patents by PatentIndex Score
19 records- 0194US7094060B2Via providing multiple electrically conductive pathsBROADCOM CORP·Filed 2005·Granted Aug 22, 2006·27 cites·25 claims
- 0293US7326061B2Via providing multiple electrically conductive pathsBROADCOM CORP·Filed 2006·Granted Feb 5, 2008·22 cites·8 claims
- 0393US7168957B2Via providing multiple electrically conductive pathsBROADCOM CORP·Filed 2006·Granted Jan 30, 2007·21 cites·23 claims
- 0491US7259448B2Die-up ball grid array package with a heat spreader and method for making the sameBROADCOM CORP·Filed 2001·Granted Aug 21, 2007·61 cites·14 claims
- 0589US7259457B2Die-up ball grid array package including a substrate capable of mounting an integrated circuit die and method for making the sameBROADCOM CORP·Filed 2004·Granted Aug 21, 2007·46 cites·21 claims
- 0686US6848912B2Via providing multiple electrically conductive paths through a circuit boardBROADCOM CORP·Filed 2002·Granted Feb 1, 2005·27 cites·38 claims
- 0783US7411281B2Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the sameBROADCOM CORP·Filed 2004·Granted Aug 12, 2008·32 cites·21 claims
- 0880US7704800B2Semiconductor assembly with one metal layer after base metal removalBROADCOM CORP·Filed 2007·Granted Apr 27, 2010·8 cites·20 claims
- 0978US7985631B2Semiconductor assembly with one metal layer after base metal removalBROADCOM CORP·Filed 2010·Granted Jul 26, 2011·4 cites·22 claims
- 1067US7595227B2Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the sameBROADCOM CORP·Filed 2008·Granted Sep 29, 2009·3 cites·16 claims
- 1163US9237651B2Padless viaBROADCOM CORP·Filed 2014·Granted Jan 12, 2016·1 cites·17 claims
- 1255US12388059B2Chip package structure and chip packaging methodHUAWEI TECH CO LTD·Filed 2021·Granted Aug 12, 2025·0 cites·20 claims
- 1353US12400982B2Chip package on package structure, packaging method thereof, and electronic deviceHUAWEI TECH CO LTD·Filed 2022·Granted Aug 26, 2025·0 cites·20 claims
- 1453US2023012986A1Chip structure and chip preparation methodHUAWEI TECH CO LTD·Filed 2022·Application pending·0 cites
- 1551US2022189901A1Multi-side power delivery in stacked memory packagingHUAWEI TECH CO LTD·Filed 2022·Application pending·0 cites
- 1651US2008169124A1Padless via and method for making sameZHANG TONGLONG·Filed 2007·Application pending·0 cites
- 1745US2009236724A1Ic package with wirebond and flipchip interconnects on the same die with through wafer viaBROADCOM CORP·Filed 2008·Application pending·0 cites
- 1845US2009200682A1Via in via circuit board structureBROADCOM CORP·Filed 2008·Application pending·0 cites
- 1938US2001002320A1Extended lead packageST ASSEMBLY TEST SERVICES PTE·Filed 2000·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →