Padless via and method for making same

Abstract

One disclosed embodiment comprises formation of a padless via in a substrate. The padless via includes a hole through a metal layer blanketing the substrate, as well as the underlying substrate. An inner wall of the padless via hole receives a seed layer of a conductive material. Electrolytic differential plating is then performed, resulting in a preferential accumulation of a conductive plating material on the via inner wall, relative to that deposited on a surface of the substrate. In one embodiment, the differential plating is performed by addition of an organic suppressant to a plating bath.

1 . A method for fabricating a via in a substrate, said method comprising:
 forming a blanket metal layer on a surface of said substrate;   drilling a via hole through said blanket metal layer and said substrate;   performing a differential plating so as to preferentially cover an inner wall of said via hole with conductive plating material, relative to said surface of said substrate.   
   
   
       2 . The method of  claim 1  further comprising patterning said surface of said substrate to leave at least one conductive tracing electrically connected to said inner wall of said via hole, so as to form a padless via. 
   
   
       3 . The method of  claim 1  further comprising applying a seed layer to said inner wall of said via hole prior to said performing said differential plating. 
   
   
       4 . The method of  claim 3  wherein said seed layer is applied electrolessly. 
   
   
       5 . The method of  claim 3  wherein said seed layer is applied electrolytically. 
   
   
       6 . The method of  claim 1  wherein said differential plating is performed electrolytically. 
   
   
       7 . The method of  claim 1  wherein said differential plating is performed by addition of an organic suppressant to a plating bath. 
   
   
       8 . The method of  claim 1  wherein said differential plating is performed anisotropically. 
   
   
       9 . The method of  claim 1  wherein said substrate is a circuit board. 
   
   
       10 . The method of  claim 1  wherein said substrate is a die package substrate. 
   
   
       11 . The method of  claim 1  wherein said conductive plating material comprises copper. 
   
   
       12 . The method of  claim 1  wherein said conductive plating material comprises a copper alloy. 
   
   
       13 . A padless via in a substrate, said padless via comprising:
 a via hole having an inner wall, said inner wall having a conductive lining;   said conductive lining defining an inner conductive ring at a surface of said substrate,   wherein said inner conductive ring is in direct electrical contact with conductive tracings on said surface of said substrate.   
   
   
       14 . The padless via of  claim 13  wherein said substrate is a circuit board. 
   
   
       15 . The padless via of  claim 13  wherein said substrate is a die package substrate. 
   
   
       16 . The padless via of  claim 13  wherein said via hole is partially filled with said conductive lining. 
   
   
       17 . The padless via of  claim 13  wherein said via hole is completely filled with said conductive lining. 
   
   
       18 . The padless via of  claim 13  wherein said conductive lining comprises copper. 
   
   
       19 . The padless via of  claim 13  wherein said conductive lining comprises a copper alloy. 
   
   
       20 . The padless via of  claim 13  wherein said conductive lining is formed by differential plating performed by addition of an organic suppressant to a plating bath.