Via in via circuit board structure

Abstract

Methods, systems, and apparatuses for electrical connections through circuit boards are described. A via-in-via structure in a circuit board provides two electrical signal paths. The circuit board includes a dielectric layer having opposing first and second planar surfaces. A first opening extends through the dielectric layer. An electrically conductive coating coats a surface of the dielectric layer in the first opening. An electrically insulating material substantially fills the first opening. The circuit board includes a first additional dielectric layer attached to the first planar surface, and a second additional dielectric layer attached to the second planar surface. A second opening extends through the first additional dielectric layer, the electrically insulating material filling the first opening, and the second additional dielectric layer. An electrically conductive material coats a surface of the first additional dielectric layer, the electrically insulating material, and the second additional dielectric layer in the second opening.

1 . A method of forming an integrated circuit package, comprising:
 forming a first opening that extends through at least one dielectric layer having opposing first and second planar surfaces;   coating a surface of the at least one dielectric layer within the first opening with an electrically conductive material;   filling the first opening with an electrically insulating material;   attaching a surface of a first at least one additional dielectric layer to the first planar surface, the surface of the first at least one additional dielectric layer having a width substantially equal to a width of the first planar surface;   attaching a second at least one additional dielectric layer to the second planar surface;   forming a second opening that extends through the first at least one additional dielectric layer, the electrically insulating material filling the first opening, and the second at least one additional dielectric layer;   coating a surface of the first at least one additional dielectric layer, the electrically insulating material filling the first opening, and the second at least one additional dielectric layer within the second opening with the electrically conductive material;   mounting an integrated circuit chip to a planar surface of the first at least one additional dielectric layer; and   attaching a plurality of electrical mounting members to a planar surface of the second at least one additional dielectric layer.   
   
   
       2 . The method of  claim 1 , wherein said coating a surface of the at least one dielectric layer within the first opening with an electrically conductive material comprises:
 forming a first via pad around the first opening on the first planar surface of the at least one dielectric layer; and   forming a second via pad around the first opening on the second planar surface of the at least one dielectric layer.   
   
   
       3 . The method of  claim 1 , wherein said coating a surface of the first at least one additional dielectric layer, the electrically insulating material filling the first opening, and the second at least one additional dielectric layer within the second opening with the electrically conductive material comprises:
 forming a third via pad around the second opening on a surface of the first at least one additional dielectric layer; and   forming a fourth via pad around the second opening on a surface of the second at least one additional dielectric layer.   
   
   
       4 . The method of  claim 3 , further comprising:
 coupling a first electrical signal net to the third via pad; and   coupling a second electrical signal net to at least one of the first and second via pads.   
   
   
       5 . The method of  claim 4 , wherein the second electrical signal net comprises a ground plane, wherein said coupling a second electrical signal net to at least one of the first and second via pads comprises:
 coupling the ground plane to at least one of the first and second via pads.   
   
   
       6 . The method of  claim 1 , further comprising:
 attaching a third at least one additional dielectric layer to a surface of the first at least one additional dielectric layer.   
   
   
       7 . The method of  claim 1 , further comprising:
 removing electrically insulating material protruding from the first opening so that the electrically insulating material is substantially planar with at least one of the first and second planar surfaces.   
   
   
       8 . An integrated circuit package formed according to the method of  claim 1 . 
   
   
       9 . An integrated circuit package, comprising:
 at least one dielectric layer having opposing first and second planar surfaces;   a first opening that extends through the at least one dielectric layer;   an electrically conductive coating within the first opening on a surface of the at least one dielectric layer;   an electrically insulating material that substantially fills the first opening;   a first at least one additional dielectric layer attached to the first planar surface, a surface of the first at least one additional dielectric layer attached to the first planar surface having a width substantially equal to a width of the first planar surface;   a second at least one additional dielectric layer attached to the second planar surface;   a second opening that extends through the first at least one additional dielectric layer, the electrically insulating material filling the first opening, and the second at least one additional dielectric layer;   an electrically conductive material within the second opening on a surface of the first at least one additional dielectric layer, the electrically insulating material, and the second at least one additional dielectric layer;   an integrated circuit chip mounted to a planar surface of the first at least one additional dielectric layer; and   a plurality of electrical mounting members attached to a planar surface of the second at least one additional dielectric layer.   
   
   
       10 . The integrated circuit package of  claim 9 , further comprising:
 a first via pad on the first planar surface of the at least one dielectric layer around the first opening; and   a second via pad on the second planar surface of the at least one dielectric layer around the first opening.   
   
   
       11 . The integrated circuit package of  claim 10 , further comprising:
 a third via pad on a surface of the first at least one additional dielectric layer around the second opening; and   a fourth via pad on a surface of the second at least one additional dielectric layer around the second opening.   
   
   
       12 . The integrated circuit package of  claim 11 , further comprising:
 a first electrical signal net coupled to the third via pad; and   a second electrical signal net coupled to at least one of the first and second via pads.   
   
   
       13 . The integrated circuit package of  claim 12 , wherein the second electrical signal net comprises a ground plane. 
   
   
       14 . The integrated circuit package of  claim 9 , further comprising:
 a third at least one additional dielectric layer attached to a surface of the first at least one additional dielectric layer.   
   
   
       15 . (canceled) 
   
   
       16 . (canceled) 
   
   
       17 . The integrated circuit package of  claim 9 , wherein the at least one dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the circuit board further comprises:
 an electrically conductive layer between the first dielectric layer and the second dielectric layer.   
   
   
       18 . The integrated circuit package of  claim 17 , wherein the electrically conductive layer is a ground layer. 
   
   
       19 . The method of  claim 1 , wherein the plurality of electrical mounting members comprises a plurality of solder balls, wherein said attaching a plurality of electrical mounting members to a planar surface of the second at least one additional dielectric layer comprises:
 attaching the plurality of solder balls to the planar surface of the second at least one additional dielectric layer.   
   
   
       20 . The integrated circuit package of  claim 9 , wherein the plurality of electrical mounting members comprises a plurality of solder balls.