Inventor · disambiguated record
Andrew Collins
Also filed as: COLLINS ANDREW · COLLINS ANDREW P · COLLINS ANDREW PAUL
28 granted patents·22 pending applications·51 citations·filing 2011–2025
94Inventor score
Top patents by PatentIndex Score
50 records- 0197US11270942B2Pitch translation architecture for semiconductor package including embedded interconnect bridgeINTEL CORP·Filed 2020·Granted Mar 8, 2022·4 cites·17 claims
- 0297US10847467B2Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling sameINTEL CORP·Filed 2019·Granted Nov 24, 2020·21 cites·20 claims
- 0396US12051647B2Pitch translation architecture for semiconductor package including embedded interconnect bridgeINTEL CORP·Filed 2023·Granted Jul 30, 2024·2 cites·17 claims
- 0496US11705398B2Pitch translation architecture for semiconductor package including embedded interconnect bridgeINTEL CORP·Filed 2022·Granted Jul 18, 2023·3 cites·17 claims
- 0588US11728294B2Capacitor die embedded in package substrate for providing capacitance to surface mounted dieINTEL CORP·Filed 2021·Granted Aug 15, 2023·1 cites·22 claims
- 0687US12388019B2Pitch translation architecture for semiconductor package including embedded interconnect bridgeINTEL CORP·Filed 2024·Granted Aug 12, 2025·0 cites·20 claims
- 0786US10490503B2Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling sameINTEL CORP·Filed 2018·Granted Nov 26, 2019·4 cites·26 claims
- 0885US11562993B2Embedded memory device and method for embedding memory device in a substrateINTEL CORP·Filed 2021·Granted Jan 24, 2023·1 cites·18 claims
- 0984US12347780B2Integrated circuit package with flipped high bandwidth memory deviceINTEL CORP·Filed 2021·Granted Jul 1, 2025·1 cites·20 claims
- 1084US2024321785A1Capacitor die embedded in package substrate for providing capacitance to surface mounted dieINTEL CORP·Filed 2024·Application pending·0 cites
- 1183US10643945B2Pitch translation architecture for semiconductor package including embedded interconnect bridgeINTEL CORP·Filed 2017·Granted May 5, 2020·2 cites·20 claims
- 1282US12046568B2Capacitor die embedded in package substrate for providing capacitance to surface mounted dieINTEL CORP·Filed 2023·Granted Jul 23, 2024·0 cites·20 claims
- 1379US2025112209A1Semiconductor packages with chiplets coupled to a memory deviceINTEL CORP·Filed 2024·Application pending·0 cites
- 1478US8913364B2Decoupling arrangementBARBER WILLIAM L·Filed 2011·Granted Dec 16, 2014·4 cites·26 claims
- 1577US11018124B2Embedded memory device and method for embedding memory device in a substrateINTEL CORP·Filed 2018·Granted May 25, 2021·2 cites·13 claims
- 1674US12205924B2Semiconductor packages with chiplets coupled to a memory deviceINTEL CORP·Filed 2023·Granted Jan 21, 2025·0 cites·20 claims
- 1773US12436912B2Disaggregated die with input/output (I/O) tilesINTEL CORP·Filed 2024·Granted Oct 7, 2025·0 cites·13 claims
- 1871US11610862B2Semiconductor packages with chiplets coupled to a memory deviceINTEL CORP·Filed 2018·Granted Mar 21, 2023·1 cites·24 claims
- 1971US10651117B2Low-inductance current paths for on-package power distributions and methods of assembling sameINTEL CORP·Filed 2018·Granted May 12, 2020·1 cites·18 claims
- 2070US11621223B2Interconnect hub for diesINTEL CORP·Filed 2019·Granted Apr 4, 2023·1 cites·20 claims
- 2170US11569173B2Bridge hub tiling architectureINTEL CORP·Filed 2017·Granted Jan 31, 2023·1 cites·21 claims
- 2268US2023138386A1Bridge hub tiling architectureINTEL CORP·Filed 2022·Application pending·0 cites
- 2367US9225164B2Decoupling arrangementINTEL CORP·Filed 2014·Granted Dec 29, 2015·1 cites·25 claims
- 2466US11456281B2Architecture and processes to enable high capacity memory packages through memory die stackingINTEL CORP·Filed 2018·Granted Sep 27, 2022·1 cites·16 claims
- 2562US11222837B2Low-inductance current paths for on-package power distributions and methods of assembling sameINTEL CORP·Filed 2020·Granted Jan 11, 2022·0 cites·16 claims
- 2660US2025252073A1Methods and apparatus to implement a high bandwidth memory (hbm) dieINTEL CORP·Filed 2025·Application pending·0 cites
- 2759US12512396B2Flexible die to floor planning with bump pitch scale through glass core via pitchINTEL CORP·Filed 2021·Granted Dec 30, 2025·0 cites·16 claims
- 2859US11195805B2Capacitor die embedded in package substrate for providing capacitance to surface mounted dieINTEL CORP·Filed 2018·Granted Dec 7, 2021·0 cites·20 claims
- 2957US2025194109A1Methods and architectures for hybrid solder and solderless die stackingINTEL CORP·Filed 2023·Application pending·0 cites
- 3056US2021263880A1Disaggregated die with input/output (i/o) tilesINTEL CORP·Filed 2020·Application pending·0 cites
- 3154US10015878B2Decoupling arrangementINTEL CORP·Filed 2015·Granted Jul 3, 2018·0 cites·9 claims
- 3254US2018270948A1Decoupling arrangementINTEL CORP·Filed 2017·Application pending·0 cites
- 3354US2025112160A1Interleaved power delivery to 3d die complexes above bridge chiplet without tsvINTEL CORP·Filed 2023·Application pending·0 cites
- 3451US2025142846A1Low resistance planar capacitorsINTEL CORP·Filed 2023·Application pending·0 cites
- 3551US2024114622A1Embedded passives with cavity sidewall interconnect in glass core architectureINTEL CORP·Filed 2022·Application pending·0 cites
- 3650US2023089096A1Multiple dies coupled with a glass core substrateINTEL CORP·Filed 2021·Application pending·0 cites
- 3750US2023090759A1Localized high permeability magnetic regions in glass patch for enhanced power deliveryINTEL CORP·Filed 2021·Application pending·0 cites
- 3850US2023086356A1Glass core substrate including buildups with different numbers of layersINTEL CORP·Filed 2021·Application pending·0 cites
- 3950US2023197592A1Power delivery techniques for glass substrate with high density signal viasINTEL CORP·Filed 2021·Application pending·0 cites
- 4050US2023299044A1Passive electrical components in mold metal layers of a multi-die complexINTEL CORP·Filed 2022·Application pending·0 cites
- 4149US2023197646A1Low loss microstrip and stripline routing with blind trench vias for high speed signaling on a glass coreINTEL CORP·Filed 2021·Application pending·0 cites
- 4248US11462521B2Multilevel die complex with integrated discrete passive componentsINTEL CORP·Filed 2018·Granted Oct 4, 2022·0 cites·20 claims
- 4348US11387187B2Embedded very high density (VHD) layerINTEL CORP·Filed 2018·Granted Jul 12, 2022·0 cites·25 claims
- 4448US2023097236A1Substrate layer count reduction enabled with bump pitch scale through glass core via pitchINTEL CORP·Filed 2021·Application pending·0 cites
- 4548US2023207406A1Ultra low loss and high-density routing between coresINTEL CORP·Filed 2021·Application pending·0 cites
- 4648US2023207405A1Ultra low loss routing between glass coresINTEL CORP·Filed 2021·Application pending·0 cites
- 4748US2023100576A1Thick and thin traces in a bridge with a glass coreINTEL CORP·Filed 2021·Application pending·0 cites
- 4847US2023197593A1Coupled fins with blind trench structuresINTEL CORP·Filed 2021·Application pending·0 cites
- 4946US2023207494A1Single layer and multilayer magnetic inductors between substrate coresXIE JIANYONG·Filed 2021·Application pending·0 cites
- 5042US11705390B2Variable in-plane signal to ground reference configurationsINTEL CORP·Filed 2019·Granted Jul 18, 2023·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →