Disaggregated die with input/output (i/o) tiles

Abstract

Embodiments may relate to a die with a processor. The die may include a first input/output (I/O) tile adjacent to a first side of the processor, and a second I/O tile adjacent to a second side of the processor. The first or second I/O tiles may be communicatively coupled with the processor. Other embodiments may be described or claimed.

1 . A die comprising:
 a processor;   a first input/output (I/O) tile adjacent to a first side of the processor, wherein the first I/O tile is communicatively coupled with the processor; and   a second I/O tile adjacent to a second side of the processor, wherein the second I/O tile is communicatively coupled with the processor.   
     
     
         2 . The die of  claim 1 , wherein the first I/O tile is to facilitate transmission of an electronic signal between the processor and another component of an electronic device to which the die is communicatively coupled. 
     
     
         3 . The die of  claim 1 , wherein the first side and the second side of the processor are adjacent to one another. 
     
     
         4 . The die of  claim 1 , wherein the first side and the second side of the processor are non-adjacent. 
     
     
         5 . The die of  claim 1 , wherein the processor is a processor core. 
     
     
         6 . The die of  claim 1 , wherein the first I/O tile has a same length as a length of the first side of the processor as measured in a direction parallel to the first side of the processor. 
     
     
         7 . The die of  claim 1 , wherein the first I/O tile has a greater length than a length of the first side of the processor as measured in a direction parallel to the first side of the processor. 
     
     
         8 . The die of  claim 1 , further comprising a second processor adjacent to the first I/O tile, wherein the first I/O tile is further communicatively coupled with the second processor. 
     
     
         9 . A die comprising:
 a substrate;   a processor core coupled with the substrate;   a first input/output (I/O) tile coupled with the substrate adjacent to a first side of the processor core, wherein the first I/O tile is communicatively coupled with the processor core by a first bridge; and   a second I/O tile coupled with the substrate adjacent to a second side of the processor core, wherein the second I/O tile is communicatively coupled with the processor core by a second bridge.   
     
     
         10 . The die of  claim 9 , wherein the first bridge is an embedded multi-die interconnect bridge (EMIB). 
     
     
         11 . The die of  claim 10 , wherein the EMIB is in the substrate. 
     
     
         12 . The die of  claim 9 , further comprising a second processor core coupled with the substrate, wherein the second processor core is communicatively coupled with the first I/O tile by a third bridge. 
     
     
         13 . The die of  claim 9 , wherein the first I/O tile is to facilitate communication between the processor core and a component to which the die is communicatively coupled. 
     
     
         14 . The die of  claim 13 , wherein the second I/O tile is to facilitate communication between the processor core and the component. 
     
     
         15 . An electronic device comprising:
 a printed circuit board (PCB); and   a die coupled with the PCB, wherein the die includes:
 a processor core; 
 a first input/output (I/O) tile adjacent to a first side of the processor core, wherein the first I/O tile is communicatively coupled with the processor core and is to facilitate communication between the processor core and the PCB; and 
 a second I/O tile adjacent to a second side of the processor core, wherein the second I/O tile is communicatively coupled with the processor core and is to facilitate communication between the processor core and the PCB. 
   
     
     
         16 . The electronic device of  claim 15 , wherein the first I/O tile has a same length as a length of the first side of the processor core as measured in a direction parallel to the first side of the processor core. 
     
     
         17 . The electronic device of  claim 16 , wherein the second I/O tile has a length greater than a length of the second side of the processor core as measured in a direction parallel to the second side of the processor core. 
     
     
         18 . The electronic device of  claim 15 , wherein the first I/O tile is communicatively coupled with the processor core by an embedded multi-die interconnect bridge (EMIB). 
     
     
         19 . The electronic device of  claim 18 , wherein the second I/O tile is communicatively coupled with the processor core by the EMIB. 
     
     
         20 . The electronic device of  claim 18 , wherein the second I/O tile is communicatively coupled with the processor core by a second EMIB.