Inventor · disambiguated record
Jeffrey C. Brownscheidle
Also filed as: BROWNSCHEIDLE JEFFREY C · BROWNSCHEIDLE JEFFREY CARL
22 granted patents·3 pending applications·54 citations·filing 2009–2018
92Inventor score
Technology areasG06F
Top patents by PatentIndex Score
25 records- 0196US9367322B1Age based fast instruction issueIBM·Filed 2015·Granted Jun 14, 2016·18 cites·20 claims
- 0289US8380964B2Processor including age tracking of issue queue instructionsIBM·Filed 2009·Granted Feb 19, 2013·18 cites·14 claims
- 0386US10223125B2Linkable issue queue parallel execution slice processing methodIBM·Filed 2018·Granted Mar 5, 2019·3 cites·20 claims
- 0485US9389870B1Age based fast instruction issueIBM·Filed 2015·Granted Jul 12, 2016·3 cites·1 claims
- 0579US10133581B2Linkable issue queue parallel execution slice for a processorIBM·Filed 2015·Granted Nov 20, 2018·2 cites·20 claims
- 0679US8489863B2Processor including age tracking of issue queue instructionsBISHOP JAMES WILSON·Filed 2012·Granted Jul 16, 2013·5 cites·7 claims
- 0773US10120693B2Fast multi-width instruction issue in parallel slice processorIBM·Filed 2018·Granted Nov 6, 2018·1 cites·20 claims
- 0869US10776122B2Prioritization protocols of conditional branch instructionsIBM·Filed 2018·Granted Sep 15, 2020·1 cites·15 claims
- 0967US10719056B2Merging status and control data in a reservation stationIBM·Filed 2016·Granted Jul 21, 2020·1 cites·20 claims
- 1067US9983879B2Operation of a multi-slice processor implementing dynamic switching of instruction issuance orderIBM·Filed 2016·Granted May 29, 2018·1 cites·18 claims
- 1167US9971600B2Techniques to wake-up dependent instructions for back-to-back issue in a microprocessorIBM·Filed 2015·Granted May 15, 2018·1 cites·17 claims
- 1261US10942745B2Fast multi-width instruction issue in parallel slice processorIBM·Filed 2018·Granted Mar 9, 2021·0 cites·18 claims
- 1361US9965286B2Age based fast instruction issueIBM·Filed 2017·Granted May 8, 2018·0 cites·1 claims
- 1461US9870231B2Age based fast instruction issueIBM·Filed 2017·Granted Jan 16, 2018·0 cites·1 claims
- 1558US9880850B2Age based fast instruction issueIBM·Filed 2016·Granted Jan 30, 2018·0 cites·20 claims
- 1655US9996359B2Fast multi-width instruction issue in parallel slice processorIBM·Filed 2016·Granted Jun 12, 2018·0 cites·20 claims
- 1752US2016202992A1Linkable issue queue parallel execution slice processing methodIBM·Filed 2015·Application pending·0 cites
- 1850US10078516B2Techniques to wake-up dependent instructions for back-to-back issue in a microprocessorIBM·Filed 2015·Granted Sep 18, 2018·0 cites·9 claims
- 1950US2016371090A1Techniques for improving issue of instructions with variable latencies in a microprocessorIBM·Filed 2016·Application pending·0 cites
- 2048US2016371091A1Techniques for improving issue of instructions with variable latencies in a microprocessorIBM·Filed 2015·Application pending·0 cites
- 2146US10031757B2Operation of a multi-slice processor implementing a mechanism to overcome a system hangIBM·Filed 2016·Granted Jul 24, 2018·0 cites·20 claims
- 2243US10740107B2Operation of a multi-slice processor implementing load-hit-store handlingIBM·Filed 2016·Granted Aug 11, 2020·0 cites·17 claims
- 2343US10445100B2Broadcasting messages between execution slices for issued instructions indicating when execution results are readyIBM·Filed 2016·Granted Oct 15, 2019·0 cites·17 claims
- 2442US11150909B2Energy efficient source operand issueIBM·Filed 2015·Granted Oct 19, 2021·0 cites·20 claims
- 2541US10318294B2Operation of a multi-slice processor implementing dependency accumulation instruction sequencingIBM·Filed 2016·Granted Jun 11, 2019·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →