US10445100B2ActiveUtilityA1

Broadcasting messages between execution slices for issued instructions indicating when execution results are ready

Assignee: IBMPriority: Jun 9, 2016Filed: Jun 9, 2016Granted: Oct 15, 2019
Est. expiryJun 9, 2036(~9.9 yrs left)· nominal 20-yr term from priority
G06F 9/3838G06F 9/3828G06F 9/3891G06F 9/3836
43
PatentIndex Score
0
Cited by
17
References
17
Claims

Abstract

Methods and apparatus for transmitting data between execution slices of a multi-slice processor including receiving, by an execution slice, a broadcast message comprising an instruction tag (ITAG) for a producer instruction, a latency, and a source identifier; determining that an issue queue in the execution slice comprises an ITAG for a consumer instruction, wherein the consumer instruction depends on result data from the producer instruction; calculating a cycle countdown using the latency and the source identifier; determining that the cycle countdown has expired; and in response to determining that the cycle countdown has expired, reading the result data from the producer instruction.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method for transmitting data between execution slices of a multi-slice processor, the method comprising:
 receiving, by an execution slice, a broadcast message originating from a source execution slice, the broadcast message comprising an instruction tag (ITAG) for a producer instruction, a latency, and a source identifier; 
 determining that an issue queue in the execution slice comprises an ITAG for a consumer instruction, wherein the consumer instruction depends on result data from the producer instruction; 
 calculating a cycle countdown using the latency and the source identifier, including:
 obtaining a cycle distance between the execution slice and a location identified by the source identifier, the location corresponding to an address of the source execution slice, wherein obtaining the cycle distance comprises dividing a physical distance between the execution slice and the source execution slice by a distance that the result data is able to traverse each cycle, wherein the cycle distance is a non-zero number of cycles required for the result data to travel from the location identified by the source identifier to the execution slice; and 
 combining the cycle distance and the latency to obtain the cycle countdown; 
 
 determining that the cycle countdown has expired; and 
 in response to determining that the cycle countdown has expired, reading the result data from the producer instruction. 
 
     
     
       2. The method of  claim 1 , wherein the cycle countdown is stored in an execution result vector by setting a flag corresponding to a value of the cycle countdown. 
     
     
       3. The method of  claim 2 , wherein the execution result vector is decremented each cycle by altering a location of the flag corresponding to the value of the cycle countdown. 
     
     
       4. The method of  claim 1 , wherein determining that the cycle countdown has expired comprises determining that a flag has been set in a ready vector corresponding to the producer instruction. 
     
     
       5. The method of  claim 1 , wherein the result data is transmitted from the source execution slice using a result bus, and wherein reading the result data from the producer instruction comprises reading the result data from the result bus. 
     
     
       6. The method of  claim 1  further comprising:
 using the result data as input for the consumer instruction. 
 
     
     
       7. A multi-slice computer processor for transmitting data between execution slices of a multi-slice processor, the multi-slice computer processor configured for:
 receiving, by an execution slice, a broadcast message originating from a source execution slice, the broadcast message comprising an instruction tag (ITAG) for a producer instruction, a latency, and a source identifier; 
 determining that an issue queue in the execution slice comprises an ITAG for a consumer instruction, wherein the consumer instruction depends on result data from the producer instruction; 
 calculating a cycle countdown using the latency and the source identifier, including:
 obtaining a cycle distance between the execution slice and a location identified by the source identifier, the location corresponding to an address of the source execution slice, wherein obtaining the cycle distance comprises dividing a physical distance between the execution slice and the source execution slice by a distance that the result data is able to traverse each cycle, wherein the cycle distance is a non-zero number of cycles required for the result data to travel from the location identified by the source identifier to the execution slice; and 
 combining the cycle distance and the latency to obtain the cycle countdown; 
 
 determining that the cycle countdown has expired; and 
 in response to determining that the cycle countdown has expired, reading the result data from the producer instruction. 
 
     
     
       8. The multi-slice computer processor of  claim 7 , wherein the cycle countdown is stored in an execution result vector by setting a flag corresponding to a value of the cycle countdown. 
     
     
       9. The multi-slice computer processor of  claim 8 , wherein the execution result vector is decremented each cycle by altering a location of the flag corresponding to the value of the cycle countdown. 
     
     
       10. The multi-slice computer processor of  claim 7 , wherein determining that the cycle countdown has expired comprises determining that a flag has been set in a ready vector corresponding to the producer instruction. 
     
     
       11. The multi-slice computer processor of  claim 7 , wherein the result data is transmitted from the source execution slice using a result bus, and wherein reading the result data from the producer instruction comprises reading the result data from the result bus. 
     
     
       12. The multi-slice computer processor of  claim 7 , wherein the multi-slice computer processor is further configured for:
 using the result data as input for the consumer instruction. 
 
     
     
       13. A computing system, the computing system including a multi-slice computer processor for transmitting data between execution slices of a multi-slice processor, the multi-slice computer processor configured for:
 receiving, by an execution slice, a broadcast message originating from a source execution slice, the broadcast message comprising an instruction tag (ITAG) for a producer instruction, a latency, and a source identifier; 
 determining that an issue queue in the execution slice comprises an ITAG for a consumer instruction, wherein the consumer instruction depends on result data from the producer instruction; 
 calculating a cycle countdown using the latency and the source identifier, including:
 obtaining a cycle distance between the execution slice and a location identified by the source identifier, the location corresponding to an address of the source execution slice, wherein obtaining the cycle distance comprises dividing a physical distance between the execution slice and the source execution slice by a distance that the result data is able to traverse each cycle, wherein the cycle distance is a non-zero number of cycles required for the result data to travel from the location identified by the source identifier to the execution slice; and 
 combining the cycle distance and the latency to obtain the cycle countdown; 
 
 determining that the cycle countdown has expired; and 
 in response to determining that the cycle countdown has expired, reading the result data from the producer instruction. 
 
     
     
       14. The computing system of  claim 13 , wherein the cycle countdown is stored in an execution result vector by setting a flag corresponding to a value of the cycle countdown. 
     
     
       15. The computing system of  claim 14 , wherein the execution result vector is decremented each cycle by altering a location of the flag corresponding to the value of the cycle countdown. 
     
     
       16. The computing system of  claim 13 , wherein determining that the cycle countdown has expired comprises determining that a flag has been set in a ready vector corresponding to the producer instruction. 
     
     
       17. The computing system of  claim 13 , wherein the result data is transmitted from the source execution slice using a result bus, and wherein reading the result data from the producer instruction comprises reading the result data from the result bus.

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